blob: da49c96ed5e365a3acb3298ca69b83dbb923288c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassb94dc892015-03-05 12:25:25 -07002/*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassb94dc892015-03-05 12:25:25 -07005 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glassb94dc892015-03-05 12:25:25 -070010#include <pci.h>
Simon Glassc5f053b2015-11-29 13:18:03 -070011#include <asm/io.h>
Simon Glassb94dc892015-03-05 12:25:25 -070012#include <dm/device-internal.h>
Simon Glass89d83232017-05-18 20:09:51 -060013#include <dm/lists.h>
Bin Mengc0820a42015-08-20 06:40:23 -070014#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
15#include <asm/fsp/fsp_support.h>
16#endif
Simon Glass37a3f94b2015-11-29 13:17:49 -070017#include "pci_internal.h"
Simon Glassb94dc892015-03-05 12:25:25 -070018
19DECLARE_GLOBAL_DATA_PTR;
20
Simon Glass2e4e4432016-01-18 20:19:14 -070021int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass7d07e592015-08-31 18:55:35 -060022{
23 int ret;
24
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
26
27 /* Since buses may not be numbered yet try a little harder with bus 0 */
28 if (ret == -ENODEV) {
Simon Glassc7298e72016-02-11 13:23:26 -070029 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass7d07e592015-08-31 18:55:35 -060030 if (ret)
31 return ret;
Simon Glass7d07e592015-08-31 18:55:35 -060032 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
33 }
34
35 return ret;
36}
37
Simon Glass6256d672015-11-19 20:27:00 -070038struct udevice *pci_get_controller(struct udevice *dev)
39{
40 while (device_is_on_pci_bus(dev))
41 dev = dev->parent;
42
43 return dev;
44}
45
Simon Glasseaa14892015-11-29 13:17:47 -070046pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glassc9118d42015-07-06 16:47:46 -060047{
48 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
49 struct udevice *bus = dev->parent;
50
51 return PCI_ADD_BUS(bus->seq, pplat->devfn);
52}
53
Simon Glassb94dc892015-03-05 12:25:25 -070054/**
55 * pci_get_bus_max() - returns the bus number of the last active bus
56 *
57 * @return last bus number, or -1 if no active buses
58 */
59static int pci_get_bus_max(void)
60{
61 struct udevice *bus;
62 struct uclass *uc;
63 int ret = -1;
64
65 ret = uclass_get(UCLASS_PCI, &uc);
66 uclass_foreach_dev(bus, uc) {
67 if (bus->seq > ret)
68 ret = bus->seq;
69 }
70
71 debug("%s: ret=%d\n", __func__, ret);
72
73 return ret;
74}
75
76int pci_last_busno(void)
77{
Bin Meng5bc3f8a2015-10-01 00:36:01 -070078 return pci_get_bus_max();
Simon Glassb94dc892015-03-05 12:25:25 -070079}
80
81int pci_get_ff(enum pci_size_t size)
82{
83 switch (size) {
84 case PCI_SIZE_8:
85 return 0xff;
86 case PCI_SIZE_16:
87 return 0xffff;
88 default:
89 return 0xffffffff;
90 }
91}
92
Marek Vasutb4535792018-10-10 21:27:06 +020093static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
94 ofnode *rnode)
95{
96 struct fdt_pci_addr addr;
97 ofnode node;
98 int ret;
99
100 dev_for_each_subnode(node, bus) {
101 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
102 &addr);
103 if (ret)
104 continue;
105
106 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
107 continue;
108
109 *rnode = node;
110 break;
111 }
112};
113
Simon Glassb94dc892015-03-05 12:25:25 -0700114int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
115 struct udevice **devp)
116{
117 struct udevice *dev;
118
119 for (device_find_first_child(bus, &dev);
120 dev;
121 device_find_next_child(&dev)) {
122 struct pci_child_platdata *pplat;
123
124 pplat = dev_get_parent_platdata(dev);
125 if (pplat && pplat->devfn == find_devfn) {
126 *devp = dev;
127 return 0;
128 }
129 }
130
131 return -ENODEV;
132}
133
Simon Glass84283d52015-11-29 13:17:48 -0700134int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassb94dc892015-03-05 12:25:25 -0700135{
136 struct udevice *bus;
137 int ret;
138
Simon Glass7d07e592015-08-31 18:55:35 -0600139 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700140 if (ret)
141 return ret;
142 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
143}
144
145static int pci_device_matches_ids(struct udevice *dev,
146 struct pci_device_id *ids)
147{
148 struct pci_child_platdata *pplat;
149 int i;
150
151 pplat = dev_get_parent_platdata(dev);
152 if (!pplat)
153 return -EINVAL;
154 for (i = 0; ids[i].vendor != 0; i++) {
155 if (pplat->vendor == ids[i].vendor &&
156 pplat->device == ids[i].device)
157 return i;
158 }
159
160 return -EINVAL;
161}
162
163int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
164 int *indexp, struct udevice **devp)
165{
166 struct udevice *dev;
167
168 /* Scan all devices on this bus */
169 for (device_find_first_child(bus, &dev);
170 dev;
171 device_find_next_child(&dev)) {
172 if (pci_device_matches_ids(dev, ids) >= 0) {
173 if ((*indexp)-- <= 0) {
174 *devp = dev;
175 return 0;
176 }
177 }
178 }
179
180 return -ENODEV;
181}
182
183int pci_find_device_id(struct pci_device_id *ids, int index,
184 struct udevice **devp)
185{
186 struct udevice *bus;
187
188 /* Scan all known buses */
189 for (uclass_first_device(UCLASS_PCI, &bus);
190 bus;
191 uclass_next_device(&bus)) {
192 if (!pci_bus_find_devices(bus, ids, &index, devp))
193 return 0;
194 }
195 *devp = NULL;
196
197 return -ENODEV;
198}
199
Simon Glass70e0c582015-11-29 13:17:50 -0700200static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
201 unsigned int device, int *indexp,
202 struct udevice **devp)
203{
204 struct pci_child_platdata *pplat;
205 struct udevice *dev;
206
207 for (device_find_first_child(bus, &dev);
208 dev;
209 device_find_next_child(&dev)) {
210 pplat = dev_get_parent_platdata(dev);
211 if (pplat->vendor == vendor && pplat->device == device) {
212 if (!(*indexp)--) {
213 *devp = dev;
214 return 0;
215 }
216 }
217 }
218
219 return -ENODEV;
220}
221
222int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
223 struct udevice **devp)
224{
225 struct udevice *bus;
226
227 /* Scan all known buses */
228 for (uclass_first_device(UCLASS_PCI, &bus);
229 bus;
230 uclass_next_device(&bus)) {
231 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
232 return device_probe(*devp);
233 }
234 *devp = NULL;
235
236 return -ENODEV;
237}
238
Simon Glassb639d512015-11-29 13:17:52 -0700239int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
240{
241 struct udevice *dev;
242
243 /* Scan all known buses */
244 for (pci_find_first_device(&dev);
245 dev;
246 pci_find_next_device(&dev)) {
247 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
248
249 if (pplat->class == find_class && !index--) {
250 *devp = dev;
251 return device_probe(*devp);
252 }
253 }
254 *devp = NULL;
255
256 return -ENODEV;
257}
258
Simon Glassb94dc892015-03-05 12:25:25 -0700259int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
260 unsigned long value, enum pci_size_t size)
261{
262 struct dm_pci_ops *ops;
263
264 ops = pci_get_ops(bus);
265 if (!ops->write_config)
266 return -ENOSYS;
267 return ops->write_config(bus, bdf, offset, value, size);
268}
269
Simon Glass9cec2df2016-03-06 19:27:52 -0700270int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
271 u32 clr, u32 set)
272{
273 ulong val;
274 int ret;
275
276 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
277 if (ret)
278 return ret;
279 val &= ~clr;
280 val |= set;
281
282 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
283}
284
Simon Glassb94dc892015-03-05 12:25:25 -0700285int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
286 enum pci_size_t size)
287{
288 struct udevice *bus;
289 int ret;
290
Simon Glass7d07e592015-08-31 18:55:35 -0600291 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700292 if (ret)
293 return ret;
294
Bin Meng0a721522015-07-19 00:20:04 +0800295 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassb94dc892015-03-05 12:25:25 -0700296}
297
Simon Glass94ef2422015-08-10 07:05:03 -0600298int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
299 enum pci_size_t size)
300{
301 struct udevice *bus;
302
Bin Meng05bedb12015-09-11 03:24:34 -0700303 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass94ef2422015-08-10 07:05:03 -0600304 bus = bus->parent;
Simon Glasseaa14892015-11-29 13:17:47 -0700305 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
306 size);
Simon Glass94ef2422015-08-10 07:05:03 -0600307}
308
Simon Glassb94dc892015-03-05 12:25:25 -0700309int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
310{
311 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
312}
313
314int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
315{
316 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
317}
318
319int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
320{
321 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
322}
323
Simon Glass94ef2422015-08-10 07:05:03 -0600324int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
325{
326 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
327}
328
329int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
330{
331 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
332}
333
334int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
335{
336 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
337}
338
Simon Glassb94dc892015-03-05 12:25:25 -0700339int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
340 unsigned long *valuep, enum pci_size_t size)
341{
342 struct dm_pci_ops *ops;
343
344 ops = pci_get_ops(bus);
345 if (!ops->read_config)
346 return -ENOSYS;
347 return ops->read_config(bus, bdf, offset, valuep, size);
348}
349
350int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
351 enum pci_size_t size)
352{
353 struct udevice *bus;
354 int ret;
355
Simon Glass7d07e592015-08-31 18:55:35 -0600356 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700357 if (ret)
358 return ret;
359
Bin Meng0a721522015-07-19 00:20:04 +0800360 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassb94dc892015-03-05 12:25:25 -0700361}
362
Simon Glass94ef2422015-08-10 07:05:03 -0600363int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
364 enum pci_size_t size)
365{
366 struct udevice *bus;
367
Bin Meng05bedb12015-09-11 03:24:34 -0700368 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass94ef2422015-08-10 07:05:03 -0600369 bus = bus->parent;
Simon Glasseaa14892015-11-29 13:17:47 -0700370 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass94ef2422015-08-10 07:05:03 -0600371 size);
372}
373
Simon Glassb94dc892015-03-05 12:25:25 -0700374int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
375{
376 unsigned long value;
377 int ret;
378
379 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
380 if (ret)
381 return ret;
382 *valuep = value;
383
384 return 0;
385}
386
387int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
388{
389 unsigned long value;
390 int ret;
391
392 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
393 if (ret)
394 return ret;
395 *valuep = value;
396
397 return 0;
398}
399
400int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
401{
402 unsigned long value;
403 int ret;
404
405 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
406 if (ret)
407 return ret;
408 *valuep = value;
409
410 return 0;
411}
412
Simon Glass94ef2422015-08-10 07:05:03 -0600413int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
414{
415 unsigned long value;
416 int ret;
417
418 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
419 if (ret)
420 return ret;
421 *valuep = value;
422
423 return 0;
424}
425
426int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
427{
428 unsigned long value;
429 int ret;
430
431 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
432 if (ret)
433 return ret;
434 *valuep = value;
435
436 return 0;
437}
438
439int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
440{
441 unsigned long value;
442 int ret;
443
444 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
445 if (ret)
446 return ret;
447 *valuep = value;
448
449 return 0;
450}
451
Simon Glass9cec2df2016-03-06 19:27:52 -0700452int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
453{
454 u8 val;
455 int ret;
456
457 ret = dm_pci_read_config8(dev, offset, &val);
458 if (ret)
459 return ret;
460 val &= ~clr;
461 val |= set;
462
463 return dm_pci_write_config8(dev, offset, val);
464}
465
466int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
467{
468 u16 val;
469 int ret;
470
471 ret = dm_pci_read_config16(dev, offset, &val);
472 if (ret)
473 return ret;
474 val &= ~clr;
475 val |= set;
476
477 return dm_pci_write_config16(dev, offset, val);
478}
479
480int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
481{
482 u32 val;
483 int ret;
484
485 ret = dm_pci_read_config32(dev, offset, &val);
486 if (ret)
487 return ret;
488 val &= ~clr;
489 val |= set;
490
491 return dm_pci_write_config32(dev, offset, val);
492}
493
Bin Menga0705782015-10-01 00:36:02 -0700494static void set_vga_bridge_bits(struct udevice *dev)
495{
496 struct udevice *parent = dev->parent;
497 u16 bc;
498
499 while (parent->seq != 0) {
500 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
501 bc |= PCI_BRIDGE_CTL_VGA;
502 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
503 parent = parent->parent;
504 }
505}
506
Simon Glassb94dc892015-03-05 12:25:25 -0700507int pci_auto_config_devices(struct udevice *bus)
508{
509 struct pci_controller *hose = bus->uclass_priv;
Bin Menga0705782015-10-01 00:36:02 -0700510 struct pci_child_platdata *pplat;
Simon Glassb94dc892015-03-05 12:25:25 -0700511 unsigned int sub_bus;
512 struct udevice *dev;
513 int ret;
514
515 sub_bus = bus->seq;
516 debug("%s: start\n", __func__);
517 pciauto_config_init(hose);
518 for (ret = device_find_first_child(bus, &dev);
519 !ret && dev;
520 ret = device_find_next_child(&dev)) {
Simon Glassb94dc892015-03-05 12:25:25 -0700521 unsigned int max_bus;
Simon Glassb072d522015-09-08 17:52:47 -0600522 int ret;
Simon Glassb94dc892015-03-05 12:25:25 -0700523
Simon Glassb94dc892015-03-05 12:25:25 -0700524 debug("%s: device %s\n", __func__, dev->name);
Simon Glass37a3f94b2015-11-29 13:17:49 -0700525 ret = dm_pciauto_config_device(dev);
Simon Glassb072d522015-09-08 17:52:47 -0600526 if (ret < 0)
527 return ret;
528 max_bus = ret;
Simon Glassb94dc892015-03-05 12:25:25 -0700529 sub_bus = max(sub_bus, max_bus);
Bin Menga0705782015-10-01 00:36:02 -0700530
531 pplat = dev_get_parent_platdata(dev);
532 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
533 set_vga_bridge_bits(dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700534 }
535 debug("%s: done\n", __func__);
536
537 return sub_bus;
538}
539
Tuomas Tynkkynen8cce4cf2017-09-19 23:18:03 +0300540int pci_generic_mmap_write_config(
541 struct udevice *bus,
542 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
543 pci_dev_t bdf,
544 uint offset,
545 ulong value,
546 enum pci_size_t size)
547{
548 void *address;
549
550 if (addr_f(bus, bdf, offset, &address) < 0)
551 return 0;
552
553 switch (size) {
554 case PCI_SIZE_8:
555 writeb(value, address);
556 return 0;
557 case PCI_SIZE_16:
558 writew(value, address);
559 return 0;
560 case PCI_SIZE_32:
561 writel(value, address);
562 return 0;
563 default:
564 return -EINVAL;
565 }
566}
567
568int pci_generic_mmap_read_config(
569 struct udevice *bus,
570 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
571 pci_dev_t bdf,
572 uint offset,
573 ulong *valuep,
574 enum pci_size_t size)
575{
576 void *address;
577
578 if (addr_f(bus, bdf, offset, &address) < 0) {
579 *valuep = pci_get_ff(size);
580 return 0;
581 }
582
583 switch (size) {
584 case PCI_SIZE_8:
585 *valuep = readb(address);
586 return 0;
587 case PCI_SIZE_16:
588 *valuep = readw(address);
589 return 0;
590 case PCI_SIZE_32:
591 *valuep = readl(address);
592 return 0;
593 default:
594 return -EINVAL;
595 }
596}
597
Simon Glass37a3f94b2015-11-29 13:17:49 -0700598int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassb94dc892015-03-05 12:25:25 -0700599{
Simon Glassb94dc892015-03-05 12:25:25 -0700600 int sub_bus;
601 int ret;
602
603 debug("%s\n", __func__);
Simon Glassb94dc892015-03-05 12:25:25 -0700604
605 sub_bus = pci_get_bus_max() + 1;
606 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass37a3f94b2015-11-29 13:17:49 -0700607 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700608
609 ret = device_probe(bus);
610 if (ret) {
Simon Glass3b02d842015-09-08 17:52:48 -0600611 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassb94dc892015-03-05 12:25:25 -0700612 ret);
613 return ret;
614 }
615 if (sub_bus != bus->seq) {
616 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
617 __func__, bus->name, bus->seq, sub_bus);
618 return -EPIPE;
619 }
620 sub_bus = pci_get_bus_max();
Simon Glass37a3f94b2015-11-29 13:17:49 -0700621 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassb94dc892015-03-05 12:25:25 -0700622
623 return sub_bus;
624}
625
Simon Glass318d71c2015-07-06 16:47:44 -0600626/**
627 * pci_match_one_device - Tell if a PCI device structure has a matching
628 * PCI device id structure
629 * @id: single PCI device id structure to match
Hou Zhiqiangd19d0612017-03-22 16:07:24 +0800630 * @find: the PCI device id structure to match against
Simon Glass318d71c2015-07-06 16:47:44 -0600631 *
Hou Zhiqiangd19d0612017-03-22 16:07:24 +0800632 * Returns true if the finding pci_device_id structure matched or false if
633 * there is no match.
Simon Glass318d71c2015-07-06 16:47:44 -0600634 */
635static bool pci_match_one_id(const struct pci_device_id *id,
636 const struct pci_device_id *find)
637{
638 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
639 (id->device == PCI_ANY_ID || id->device == find->device) &&
640 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
641 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
642 !((id->class ^ find->class) & id->class_mask))
643 return true;
644
645 return false;
646}
647
648/**
649 * pci_find_and_bind_driver() - Find and bind the right PCI driver
650 *
651 * This only looks at certain fields in the descriptor.
Simon Glassc45abf12015-09-08 17:52:49 -0600652 *
653 * @parent: Parent bus
654 * @find_id: Specification of the driver to find
655 * @bdf: Bus/device/function addreess - see PCI_BDF()
656 * @devp: Returns a pointer to the device created
657 * @return 0 if OK, -EPERM if the device is not needed before relocation and
658 * therefore was not created, other -ve value on error
Simon Glass318d71c2015-07-06 16:47:44 -0600659 */
660static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glassc45abf12015-09-08 17:52:49 -0600661 struct pci_device_id *find_id,
662 pci_dev_t bdf, struct udevice **devp)
Simon Glass318d71c2015-07-06 16:47:44 -0600663{
664 struct pci_driver_entry *start, *entry;
Marek Vasutb4535792018-10-10 21:27:06 +0200665 ofnode node = ofnode_null();
Simon Glass318d71c2015-07-06 16:47:44 -0600666 const char *drv;
667 int n_ents;
668 int ret;
669 char name[30], *str;
Bin Meng984c0dc2015-08-20 06:40:17 -0700670 bool bridge;
Simon Glass318d71c2015-07-06 16:47:44 -0600671
672 *devp = NULL;
673
674 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
675 find_id->vendor, find_id->device);
Marek Vasutb4535792018-10-10 21:27:06 +0200676
677 /* Determine optional OF node */
678 pci_dev_find_ofnode(parent, bdf, &node);
679
Simon Glass318d71c2015-07-06 16:47:44 -0600680 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
681 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
682 for (entry = start; entry != start + n_ents; entry++) {
683 const struct pci_device_id *id;
684 struct udevice *dev;
685 const struct driver *drv;
686
687 for (id = entry->match;
688 id->vendor || id->subvendor || id->class_mask;
689 id++) {
690 if (!pci_match_one_id(id, find_id))
691 continue;
692
693 drv = entry->driver;
Bin Meng984c0dc2015-08-20 06:40:17 -0700694
695 /*
696 * In the pre-relocation phase, we only bind devices
697 * whose driver has the DM_FLAG_PRE_RELOC set, to save
698 * precious memory space as on some platforms as that
699 * space is pretty limited (ie: using Cache As RAM).
700 */
701 if (!(gd->flags & GD_FLG_RELOC) &&
702 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glassc45abf12015-09-08 17:52:49 -0600703 return -EPERM;
Bin Meng984c0dc2015-08-20 06:40:17 -0700704
Simon Glass318d71c2015-07-06 16:47:44 -0600705 /*
706 * We could pass the descriptor to the driver as
707 * platdata (instead of NULL) and allow its bind()
708 * method to return -ENOENT if it doesn't support this
709 * device. That way we could continue the search to
710 * find another driver. For now this doesn't seem
711 * necesssary, so just bind the first match.
712 */
Marek Vasutb4535792018-10-10 21:27:06 +0200713 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
714 node, &dev);
Simon Glass318d71c2015-07-06 16:47:44 -0600715 if (ret)
716 goto error;
717 debug("%s: Match found: %s\n", __func__, drv->name);
Bin Menga8d27802018-08-03 01:14:44 -0700718 dev->driver_data = id->driver_data;
Simon Glass318d71c2015-07-06 16:47:44 -0600719 *devp = dev;
720 return 0;
721 }
722 }
723
Bin Meng984c0dc2015-08-20 06:40:17 -0700724 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
725 /*
726 * In the pre-relocation phase, we only bind bridge devices to save
727 * precious memory space as on some platforms as that space is pretty
728 * limited (ie: using Cache As RAM).
729 */
730 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glassc45abf12015-09-08 17:52:49 -0600731 return -EPERM;
Bin Meng984c0dc2015-08-20 06:40:17 -0700732
Simon Glass318d71c2015-07-06 16:47:44 -0600733 /* Bind a generic driver so that the device can be used */
Bin Meng0a721522015-07-19 00:20:04 +0800734 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
735 PCI_FUNC(bdf));
Simon Glass318d71c2015-07-06 16:47:44 -0600736 str = strdup(name);
737 if (!str)
738 return -ENOMEM;
Bin Meng984c0dc2015-08-20 06:40:17 -0700739 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
740
Marek Vasutb4535792018-10-10 21:27:06 +0200741 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
Simon Glass318d71c2015-07-06 16:47:44 -0600742 if (ret) {
Simon Glass3b02d842015-09-08 17:52:48 -0600743 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dea89009c2017-05-08 20:40:16 +0200744 free(str);
Simon Glass318d71c2015-07-06 16:47:44 -0600745 return ret;
746 }
747 debug("%s: No match found: bound generic driver instead\n", __func__);
748
749 return 0;
750
751error:
752 debug("%s: No match found: error %d\n", __func__, ret);
753 return ret;
754}
755
Simon Glassb94dc892015-03-05 12:25:25 -0700756int pci_bind_bus_devices(struct udevice *bus)
757{
758 ulong vendor, device;
759 ulong header_type;
Bin Meng0a721522015-07-19 00:20:04 +0800760 pci_dev_t bdf, end;
Simon Glassb94dc892015-03-05 12:25:25 -0700761 bool found_multi;
762 int ret;
763
764 found_multi = false;
Bin Meng0a721522015-07-19 00:20:04 +0800765 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
766 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato1e3bce22016-04-25 15:41:01 +0900767 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng0a721522015-07-19 00:20:04 +0800768 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassb94dc892015-03-05 12:25:25 -0700769 struct pci_child_platdata *pplat;
770 struct udevice *dev;
771 ulong class;
772
Bin Meng20bdc1e2018-08-03 01:14:37 -0700773 if (!PCI_FUNC(bdf))
774 found_multi = false;
Bin Meng0a721522015-07-19 00:20:04 +0800775 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassb94dc892015-03-05 12:25:25 -0700776 continue;
777 /* Check only the first access, we don't expect problems */
Bin Meng0a721522015-07-19 00:20:04 +0800778 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassb94dc892015-03-05 12:25:25 -0700779 &header_type, PCI_SIZE_8);
780 if (ret)
781 goto error;
Bin Meng0a721522015-07-19 00:20:04 +0800782 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassb94dc892015-03-05 12:25:25 -0700783 PCI_SIZE_16);
784 if (vendor == 0xffff || vendor == 0x0000)
785 continue;
786
Bin Meng0a721522015-07-19 00:20:04 +0800787 if (!PCI_FUNC(bdf))
Simon Glassb94dc892015-03-05 12:25:25 -0700788 found_multi = header_type & 0x80;
789
790 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng0a721522015-07-19 00:20:04 +0800791 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
792 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassb94dc892015-03-05 12:25:25 -0700793 PCI_SIZE_16);
Bin Meng0a721522015-07-19 00:20:04 +0800794 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glass318d71c2015-07-06 16:47:44 -0600795 PCI_SIZE_32);
796 class >>= 8;
Simon Glassb94dc892015-03-05 12:25:25 -0700797
798 /* Find this device in the device tree */
Bin Meng0a721522015-07-19 00:20:04 +0800799 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700800
Simon Glass413ebdb2015-11-29 13:18:09 -0700801 /* If nothing in the device tree, bind a device */
Simon Glassb94dc892015-03-05 12:25:25 -0700802 if (ret == -ENODEV) {
Simon Glass318d71c2015-07-06 16:47:44 -0600803 struct pci_device_id find_id;
804 ulong val;
Simon Glassb94dc892015-03-05 12:25:25 -0700805
Simon Glass318d71c2015-07-06 16:47:44 -0600806 memset(&find_id, '\0', sizeof(find_id));
807 find_id.vendor = vendor;
808 find_id.device = device;
809 find_id.class = class;
810 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng0a721522015-07-19 00:20:04 +0800811 pci_bus_read_config(bus, bdf,
Simon Glass318d71c2015-07-06 16:47:44 -0600812 PCI_SUBSYSTEM_VENDOR_ID,
813 &val, PCI_SIZE_32);
814 find_id.subvendor = val & 0xffff;
815 find_id.subdevice = val >> 16;
816 }
Bin Meng0a721522015-07-19 00:20:04 +0800817 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glass318d71c2015-07-06 16:47:44 -0600818 &dev);
Simon Glassb94dc892015-03-05 12:25:25 -0700819 }
Simon Glassc45abf12015-09-08 17:52:49 -0600820 if (ret == -EPERM)
821 continue;
822 else if (ret)
Simon Glassb94dc892015-03-05 12:25:25 -0700823 return ret;
824
825 /* Update the platform data */
Simon Glassc45abf12015-09-08 17:52:49 -0600826 pplat = dev_get_parent_platdata(dev);
827 pplat->devfn = PCI_MASK_BUS(bdf);
828 pplat->vendor = vendor;
829 pplat->device = device;
830 pplat->class = class;
Simon Glassb94dc892015-03-05 12:25:25 -0700831 }
832
833 return 0;
834error:
835 printf("Cannot read bus configuration: %d\n", ret);
836
837 return ret;
838}
839
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700840static void decode_regions(struct pci_controller *hose, ofnode parent_node,
841 ofnode node)
Simon Glassb94dc892015-03-05 12:25:25 -0700842{
843 int pci_addr_cells, addr_cells, size_cells;
844 int cells_per_record;
845 const u32 *prop;
846 int len;
847 int i;
848
Masahiro Yamada9cf85cb2017-06-22 16:54:05 +0900849 prop = ofnode_get_property(node, "ranges", &len);
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700850 if (!prop) {
851 debug("%s: Cannot decode regions\n", __func__);
852 return;
853 }
854
Simon Glass4191dc12017-06-12 06:21:31 -0600855 pci_addr_cells = ofnode_read_simple_addr_cells(node);
856 addr_cells = ofnode_read_simple_addr_cells(parent_node);
857 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassb94dc892015-03-05 12:25:25 -0700858
859 /* PCI addresses are always 3-cells */
860 len /= sizeof(u32);
861 cells_per_record = pci_addr_cells + addr_cells + size_cells;
862 hose->region_count = 0;
863 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
864 cells_per_record);
865 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
866 u64 pci_addr, addr, size;
867 int space_code;
868 u32 flags;
869 int type;
Simon Glass7efc9ba2015-11-19 20:26:58 -0700870 int pos;
Simon Glassb94dc892015-03-05 12:25:25 -0700871
872 if (len < cells_per_record)
873 break;
874 flags = fdt32_to_cpu(prop[0]);
875 space_code = (flags >> 24) & 3;
876 pci_addr = fdtdec_get_number(prop + 1, 2);
877 prop += pci_addr_cells;
878 addr = fdtdec_get_number(prop, addr_cells);
879 prop += addr_cells;
880 size = fdtdec_get_number(prop, size_cells);
881 prop += size_cells;
Masahiro Yamadac7570a32018-08-06 20:47:40 +0900882 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
883 __func__, hose->region_count, pci_addr, addr, size, space_code);
Simon Glassb94dc892015-03-05 12:25:25 -0700884 if (space_code & 2) {
885 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
886 PCI_REGION_MEM;
887 } else if (space_code & 1) {
888 type = PCI_REGION_IO;
889 } else {
890 continue;
891 }
Tuomas Tynkkynenc307e172018-05-14 18:47:50 +0300892
893 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
894 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
895 debug(" - beyond the 32-bit boundary, ignoring\n");
896 continue;
897 }
898
Simon Glass7efc9ba2015-11-19 20:26:58 -0700899 pos = -1;
900 for (i = 0; i < hose->region_count; i++) {
901 if (hose->regions[i].flags == type)
902 pos = i;
903 }
904 if (pos == -1)
905 pos = hose->region_count++;
906 debug(" - type=%d, pos=%d\n", type, pos);
907 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassb94dc892015-03-05 12:25:25 -0700908 }
909
910 /* Add a region for our local memory */
Bernhard Messerklinger9c5df382018-02-15 08:59:53 +0100911#ifdef CONFIG_NR_DRAM_BANKS
912 bd_t *bd = gd->bd;
913
Bin Mengae0bdde2018-03-27 00:46:05 -0700914 if (!bd)
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700915 return;
Bin Mengae0bdde2018-03-27 00:46:05 -0700916
Bernhard Messerklinger9c5df382018-02-15 08:59:53 +0100917 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
918 if (bd->bi_dram[i].size) {
919 pci_set_region(hose->regions + hose->region_count++,
920 bd->bi_dram[i].start,
921 bd->bi_dram[i].start,
922 bd->bi_dram[i].size,
923 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
924 }
925 }
926#else
927 phys_addr_t base = 0, size;
928
Simon Glass91de6c52015-11-19 20:26:57 -0700929 size = gd->ram_size;
930#ifdef CONFIG_SYS_SDRAM_BASE
931 base = CONFIG_SYS_SDRAM_BASE;
932#endif
933 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
934 size = gd->pci_ram_top - base;
Bin Meng6d532072018-03-27 00:46:06 -0700935 if (size)
936 pci_set_region(hose->regions + hose->region_count++, base,
937 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Bernhard Messerklinger9c5df382018-02-15 08:59:53 +0100938#endif
Simon Glassb94dc892015-03-05 12:25:25 -0700939
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700940 return;
Simon Glassb94dc892015-03-05 12:25:25 -0700941}
942
943static int pci_uclass_pre_probe(struct udevice *bus)
944{
945 struct pci_controller *hose;
Simon Glassb94dc892015-03-05 12:25:25 -0700946
947 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
948 bus->parent->name);
949 hose = bus->uclass_priv;
950
951 /* For bridges, use the top-level PCI controller */
Paul Burtone3b106d2016-09-08 07:47:32 +0100952 if (!device_is_on_pci_bus(bus)) {
Simon Glassb94dc892015-03-05 12:25:25 -0700953 hose->ctlr = bus;
Christian Gmeiner5f4e0942018-06-10 06:25:05 -0700954 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
Simon Glassb94dc892015-03-05 12:25:25 -0700955 } else {
956 struct pci_controller *parent_hose;
957
958 parent_hose = dev_get_uclass_priv(bus->parent);
959 hose->ctlr = parent_hose->bus;
960 }
961 hose->bus = bus;
962 hose->first_busno = bus->seq;
963 hose->last_busno = bus->seq;
964
965 return 0;
966}
967
968static int pci_uclass_post_probe(struct udevice *bus)
969{
970 int ret;
971
Simon Glassb94dc892015-03-05 12:25:25 -0700972 debug("%s: probing bus %d\n", __func__, bus->seq);
973 ret = pci_bind_bus_devices(bus);
974 if (ret)
975 return ret;
976
977#ifdef CONFIG_PCI_PNP
978 ret = pci_auto_config_devices(bus);
Simon Glassb072d522015-09-08 17:52:47 -0600979 if (ret < 0)
980 return ret;
Simon Glassb94dc892015-03-05 12:25:25 -0700981#endif
982
Bin Mengc0820a42015-08-20 06:40:23 -0700983#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
984 /*
985 * Per Intel FSP specification, we should call FSP notify API to
986 * inform FSP that PCI enumeration has been done so that FSP will
987 * do any necessary initialization as required by the chipset's
988 * BIOS Writer's Guide (BWG).
989 *
990 * Unfortunately we have to put this call here as with driver model,
991 * the enumeration is all done on a lazy basis as needed, so until
992 * something is touched on PCI it won't happen.
993 *
994 * Note we only call this 1) after U-Boot is relocated, and 2)
995 * root bus has finished probing.
996 */
Simon Glassb072d522015-09-08 17:52:47 -0600997 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Mengc0820a42015-08-20 06:40:23 -0700998 ret = fsp_init_phase_pci();
Simon Glassb072d522015-09-08 17:52:47 -0600999 if (ret)
1000 return ret;
1001 }
Bin Mengc0820a42015-08-20 06:40:23 -07001002#endif
1003
Simon Glassb072d522015-09-08 17:52:47 -06001004 return 0;
Simon Glassb94dc892015-03-05 12:25:25 -07001005}
1006
1007static int pci_uclass_child_post_bind(struct udevice *dev)
1008{
1009 struct pci_child_platdata *pplat;
1010 struct fdt_pci_addr addr;
1011 int ret;
1012
Simon Glass89d83232017-05-18 20:09:51 -06001013 if (!dev_of_valid(dev))
Simon Glassb94dc892015-03-05 12:25:25 -07001014 return 0;
1015
Simon Glassb94dc892015-03-05 12:25:25 -07001016 pplat = dev_get_parent_platdata(dev);
Bin Meng00d808e2018-08-03 01:14:36 -07001017
1018 /* Extract vendor id and device id if available */
1019 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1020
1021 /* Extract the devfn from fdt_pci_addr */
Simon Glass89d83232017-05-18 20:09:51 -06001022 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
1023 &addr);
Simon Glassb94dc892015-03-05 12:25:25 -07001024 if (ret) {
1025 if (ret != -ENOENT)
1026 return -EINVAL;
1027 } else {
Bin Meng44344a62015-08-20 06:40:26 -07001028 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassb94dc892015-03-05 12:25:25 -07001029 }
1030
1031 return 0;
1032}
1033
Bin Meng0a721522015-07-19 00:20:04 +08001034static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1035 uint offset, ulong *valuep,
1036 enum pci_size_t size)
Simon Glassb94dc892015-03-05 12:25:25 -07001037{
1038 struct pci_controller *hose = bus->uclass_priv;
Simon Glassb94dc892015-03-05 12:25:25 -07001039
1040 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1041}
1042
Bin Meng0a721522015-07-19 00:20:04 +08001043static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1044 uint offset, ulong value,
1045 enum pci_size_t size)
Simon Glassb94dc892015-03-05 12:25:25 -07001046{
1047 struct pci_controller *hose = bus->uclass_priv;
Simon Glassb94dc892015-03-05 12:25:25 -07001048
1049 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1050}
1051
Simon Glass04c8b6a2015-08-10 07:05:04 -06001052static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1053{
1054 struct udevice *dev;
1055 int ret = 0;
1056
1057 /*
1058 * Scan through all the PCI controllers. On x86 there will only be one
1059 * but that is not necessarily true on other hardware.
1060 */
1061 do {
1062 device_find_first_child(bus, &dev);
1063 if (dev) {
1064 *devp = dev;
1065 return 0;
1066 }
1067 ret = uclass_next_device(&bus);
1068 if (ret)
1069 return ret;
1070 } while (bus);
1071
1072 return 0;
1073}
1074
1075int pci_find_next_device(struct udevice **devp)
1076{
1077 struct udevice *child = *devp;
1078 struct udevice *bus = child->parent;
1079 int ret;
1080
1081 /* First try all the siblings */
1082 *devp = NULL;
1083 while (child) {
1084 device_find_next_child(&child);
1085 if (child) {
1086 *devp = child;
1087 return 0;
1088 }
1089 }
1090
1091 /* We ran out of siblings. Try the next bus */
1092 ret = uclass_next_device(&bus);
1093 if (ret)
1094 return ret;
1095
1096 return bus ? skip_to_next_device(bus, devp) : 0;
1097}
1098
1099int pci_find_first_device(struct udevice **devp)
1100{
1101 struct udevice *bus;
1102 int ret;
1103
1104 *devp = NULL;
1105 ret = uclass_first_device(UCLASS_PCI, &bus);
1106 if (ret)
1107 return ret;
1108
1109 return skip_to_next_device(bus, devp);
1110}
1111
Simon Glass27a733f2015-11-19 20:26:59 -07001112ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1113{
1114 switch (size) {
1115 case PCI_SIZE_8:
1116 return (value >> ((offset & 3) * 8)) & 0xff;
1117 case PCI_SIZE_16:
1118 return (value >> ((offset & 2) * 8)) & 0xffff;
1119 default:
1120 return value;
1121 }
1122}
1123
1124ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1125 enum pci_size_t size)
1126{
1127 uint off_mask;
1128 uint val_mask, shift;
1129 ulong ldata, mask;
1130
1131 switch (size) {
1132 case PCI_SIZE_8:
1133 off_mask = 3;
1134 val_mask = 0xff;
1135 break;
1136 case PCI_SIZE_16:
1137 off_mask = 2;
1138 val_mask = 0xffff;
1139 break;
1140 default:
1141 return value;
1142 }
1143 shift = (offset & off_mask) * 8;
1144 ldata = (value & val_mask) << shift;
1145 mask = val_mask << shift;
1146 value = (old & ~mask) | ldata;
1147
1148 return value;
1149}
1150
Simon Glassdcdc0122015-11-19 20:27:01 -07001151int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1152 struct pci_region **memp, struct pci_region **prefp)
1153{
1154 struct udevice *bus = pci_get_controller(dev);
1155 struct pci_controller *hose = dev_get_uclass_priv(bus);
1156 int i;
1157
1158 *iop = NULL;
1159 *memp = NULL;
1160 *prefp = NULL;
1161 for (i = 0; i < hose->region_count; i++) {
1162 switch (hose->regions[i].flags) {
1163 case PCI_REGION_IO:
1164 if (!*iop || (*iop)->size < hose->regions[i].size)
1165 *iop = hose->regions + i;
1166 break;
1167 case PCI_REGION_MEM:
1168 if (!*memp || (*memp)->size < hose->regions[i].size)
1169 *memp = hose->regions + i;
1170 break;
1171 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1172 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1173 *prefp = hose->regions + i;
1174 break;
1175 }
1176 }
1177
1178 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1179}
1180
Simon Glass3452cb12015-11-29 13:17:53 -07001181u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1182{
1183 u32 addr;
1184 int bar;
1185
1186 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1187 dm_pci_read_config32(dev, bar, &addr);
1188 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1189 return addr & PCI_BASE_ADDRESS_IO_MASK;
1190 else
1191 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1192}
1193
Simon Glasse2b6b562016-01-18 20:19:15 -07001194void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1195{
1196 int bar;
1197
1198 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1199 dm_pci_write_config32(dev, bar, addr);
1200}
1201
Simon Glassc5f053b2015-11-29 13:18:03 -07001202static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1203 pci_addr_t bus_addr, unsigned long flags,
1204 unsigned long skip_mask, phys_addr_t *pa)
1205{
1206 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1207 struct pci_region *res;
1208 int i;
1209
Christian Gmeiner7241f802018-06-10 06:25:06 -07001210 if (hose->region_count == 0) {
1211 *pa = bus_addr;
1212 return 0;
1213 }
1214
Simon Glassc5f053b2015-11-29 13:18:03 -07001215 for (i = 0; i < hose->region_count; i++) {
1216 res = &hose->regions[i];
1217
1218 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1219 continue;
1220
1221 if (res->flags & skip_mask)
1222 continue;
1223
1224 if (bus_addr >= res->bus_start &&
1225 (bus_addr - res->bus_start) < res->size) {
1226 *pa = (bus_addr - res->bus_start + res->phys_start);
1227 return 0;
1228 }
1229 }
1230
1231 return 1;
1232}
1233
1234phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1235 unsigned long flags)
1236{
1237 phys_addr_t phys_addr = 0;
1238 struct udevice *ctlr;
1239 int ret;
1240
1241 /* The root controller has the region information */
1242 ctlr = pci_get_controller(dev);
1243
1244 /*
1245 * if PCI_REGION_MEM is set we do a two pass search with preference
1246 * on matches that don't have PCI_REGION_SYS_MEMORY set
1247 */
1248 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1249 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1250 flags, PCI_REGION_SYS_MEMORY,
1251 &phys_addr);
1252 if (!ret)
1253 return phys_addr;
1254 }
1255
1256 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1257
1258 if (ret)
1259 puts("pci_hose_bus_to_phys: invalid physical address\n");
1260
1261 return phys_addr;
1262}
1263
1264int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1265 unsigned long flags, unsigned long skip_mask,
1266 pci_addr_t *ba)
1267{
1268 struct pci_region *res;
1269 struct udevice *ctlr;
1270 pci_addr_t bus_addr;
1271 int i;
1272 struct pci_controller *hose;
1273
1274 /* The root controller has the region information */
1275 ctlr = pci_get_controller(dev);
1276 hose = dev_get_uclass_priv(ctlr);
1277
Christian Gmeiner7241f802018-06-10 06:25:06 -07001278 if (hose->region_count == 0) {
1279 *ba = phys_addr;
1280 return 0;
1281 }
1282
Simon Glassc5f053b2015-11-29 13:18:03 -07001283 for (i = 0; i < hose->region_count; i++) {
1284 res = &hose->regions[i];
1285
1286 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1287 continue;
1288
1289 if (res->flags & skip_mask)
1290 continue;
1291
1292 bus_addr = phys_addr - res->phys_start + res->bus_start;
1293
1294 if (bus_addr >= res->bus_start &&
1295 (bus_addr - res->bus_start) < res->size) {
1296 *ba = bus_addr;
1297 return 0;
1298 }
1299 }
1300
1301 return 1;
1302}
1303
1304pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1305 unsigned long flags)
1306{
1307 pci_addr_t bus_addr = 0;
1308 int ret;
1309
1310 /*
1311 * if PCI_REGION_MEM is set we do a two pass search with preference
1312 * on matches that don't have PCI_REGION_SYS_MEMORY set
1313 */
1314 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1315 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1316 PCI_REGION_SYS_MEMORY, &bus_addr);
1317 if (!ret)
1318 return bus_addr;
1319 }
1320
1321 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1322
1323 if (ret)
1324 puts("pci_hose_phys_to_bus: invalid physical address\n");
1325
1326 return bus_addr;
1327}
1328
1329void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1330{
1331 pci_addr_t pci_bus_addr;
1332 u32 bar_response;
1333
1334 /* read BAR address */
1335 dm_pci_read_config32(dev, bar, &bar_response);
1336 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1337
1338 /*
1339 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1340 * isn't actualy used on any platform because u-boot assumes a static
1341 * linear mapping. In the future, this could read the BAR size
1342 * and pass that as the size if needed.
1343 */
1344 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1345}
1346
Bin Menga7366f02018-08-03 01:14:52 -07001347int dm_pci_find_capability(struct udevice *dev, int cap)
1348{
1349 u16 status;
1350 u8 header_type;
1351 int ttl = PCI_FIND_CAP_TTL;
1352 u8 id;
1353 u16 ent;
1354 u8 pos;
1355
1356 dm_pci_read_config16(dev, PCI_STATUS, &status);
1357 if (!(status & PCI_STATUS_CAP_LIST))
1358 return 0;
1359
1360 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1361 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1362 pos = PCI_CB_CAPABILITY_LIST;
1363 else
1364 pos = PCI_CAPABILITY_LIST;
1365
1366 dm_pci_read_config8(dev, pos, &pos);
1367 while (ttl--) {
1368 if (pos < PCI_STD_HEADER_SIZEOF)
1369 break;
1370 pos &= ~3;
1371 dm_pci_read_config16(dev, pos, &ent);
1372
1373 id = ent & 0xff;
1374 if (id == 0xff)
1375 break;
1376 if (id == cap)
1377 return pos;
1378 pos = (ent >> 8);
1379 }
1380
1381 return 0;
1382}
1383
1384int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1385{
1386 u32 header;
1387 int ttl;
1388 int pos = PCI_CFG_SPACE_SIZE;
1389
1390 /* minimum 8 bytes per capability */
1391 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1392
1393 dm_pci_read_config32(dev, pos, &header);
1394 /*
1395 * If we have no capabilities, this is indicated by cap ID,
1396 * cap version and next pointer all being 0.
1397 */
1398 if (header == 0)
1399 return 0;
1400
1401 while (ttl--) {
1402 if (PCI_EXT_CAP_ID(header) == cap)
1403 return pos;
1404
1405 pos = PCI_EXT_CAP_NEXT(header);
1406 if (pos < PCI_CFG_SPACE_SIZE)
1407 break;
1408
1409 dm_pci_read_config32(dev, pos, &header);
1410 }
1411
1412 return 0;
1413}
1414
Simon Glassb94dc892015-03-05 12:25:25 -07001415UCLASS_DRIVER(pci) = {
1416 .id = UCLASS_PCI,
1417 .name = "pci",
Simon Glassa8149412015-05-10 21:08:06 -06001418 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass18230342016-07-05 17:10:10 -06001419 .post_bind = dm_scan_fdt_dev,
Simon Glassb94dc892015-03-05 12:25:25 -07001420 .pre_probe = pci_uclass_pre_probe,
1421 .post_probe = pci_uclass_post_probe,
1422 .child_post_bind = pci_uclass_child_post_bind,
1423 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1424 .per_child_platdata_auto_alloc_size =
1425 sizeof(struct pci_child_platdata),
1426};
1427
1428static const struct dm_pci_ops pci_bridge_ops = {
1429 .read_config = pci_bridge_read_config,
1430 .write_config = pci_bridge_write_config,
1431};
1432
1433static const struct udevice_id pci_bridge_ids[] = {
1434 { .compatible = "pci-bridge" },
1435 { }
1436};
1437
1438U_BOOT_DRIVER(pci_bridge_drv) = {
1439 .name = "pci_bridge_drv",
1440 .id = UCLASS_PCI,
1441 .of_match = pci_bridge_ids,
1442 .ops = &pci_bridge_ops,
1443};
1444
1445UCLASS_DRIVER(pci_generic) = {
1446 .id = UCLASS_PCI_GENERIC,
1447 .name = "pci_generic",
1448};
1449
1450static const struct udevice_id pci_generic_ids[] = {
1451 { .compatible = "pci-generic" },
1452 { }
1453};
1454
1455U_BOOT_DRIVER(pci_generic_drv) = {
1456 .name = "pci_generic_drv",
1457 .id = UCLASS_PCI_GENERIC,
1458 .of_match = pci_generic_ids,
1459};
Stephen Warren04eb2692016-01-26 11:10:11 -07001460
1461void pci_init(void)
1462{
1463 struct udevice *bus;
1464
1465 /*
1466 * Enumerate all known controller devices. Enumeration has the side-
1467 * effect of probing them, so PCIe devices will be enumerated too.
1468 */
1469 for (uclass_first_device(UCLASS_PCI, &bus);
1470 bus;
1471 uclass_next_device(&bus)) {
1472 ;
1473 }
1474}