blob: bc456bb4a9e0442e2af461c69cb04e3f3b0ff4a9 [file] [log] [blame]
Simon Glassddb39b22019-08-24 14:10:32 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
7#include <handoff.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glassddb39b22019-08-24 14:10:32 -06009#include <asm/fsp/fsp_support.h>
10#include <asm/e820.h>
11#include <asm/mrccache.h>
12#include <asm/post.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16int fsp_scan_for_ram_size(void)
17{
18 phys_size_t ram_size = 0;
19 const struct hob_header *hdr;
20 struct hob_res_desc *res_desc;
21
22 hdr = gd->arch.hob_list;
23 while (!end_of_hob(hdr)) {
24 if (hdr->type == HOB_TYPE_RES_DESC) {
25 res_desc = (struct hob_res_desc *)hdr;
26 if (res_desc->type == RES_SYS_MEM ||
27 res_desc->type == RES_MEM_RESERVED)
28 ram_size += res_desc->len;
29 }
30 hdr = get_next_hob(hdr);
31 }
32
33 gd->ram_size = ram_size;
34 post_code(POST_DRAM);
35
36 return 0;
37};
38
39int dram_init_banksize(void)
40{
41 gd->bd->bi_dram[0].start = 0;
42 gd->bd->bi_dram[0].size = gd->ram_size;
43
44 return 0;
45}
46
47unsigned int install_e820_map(unsigned int max_entries,
48 struct e820_entry *entries)
49{
50 unsigned int num_entries = 0;
51 const struct hob_header *hdr;
52 struct hob_res_desc *res_desc;
53
54 hdr = gd->arch.hob_list;
55
56 while (!end_of_hob(hdr)) {
57 if (hdr->type == HOB_TYPE_RES_DESC) {
58 res_desc = (struct hob_res_desc *)hdr;
59 entries[num_entries].addr = res_desc->phys_start;
60 entries[num_entries].size = res_desc->len;
61
62 if (res_desc->type == RES_SYS_MEM)
63 entries[num_entries].type = E820_RAM;
64 else if (res_desc->type == RES_MEM_RESERVED)
65 entries[num_entries].type = E820_RESERVED;
66
67 num_entries++;
68 }
69 hdr = get_next_hob(hdr);
70 }
71
72 /* Mark PCIe ECAM address range as reserved */
73 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
74 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
75 entries[num_entries].type = E820_RESERVED;
76 num_entries++;
77
78#ifdef CONFIG_HAVE_ACPI_RESUME
79 /*
80 * Everything between U-Boot's stack and ram top needs to be
81 * reserved in order for ACPI S3 resume to work.
82 */
83 entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
84 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
85 CONFIG_STACK_SIZE;
86 entries[num_entries].type = E820_RESERVED;
87 num_entries++;
88#endif
89
90 return num_entries;
91}
Simon Glass25628082019-09-25 08:11:41 -060092
93#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
94int handoff_arch_save(struct spl_handoff *ho)
95{
96 ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
97 ho->arch.hob_list = gd->arch.hob_list;
98
99 return 0;
100}
101#endif