blob: fcf2ec97889ddc299fa469000ea7adcb944cd6d6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wang Huanddf89f92014-09-05 13:52:45 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Wang Huanddf89f92014-09-05 13:52:45 +08004 */
5
6#include <common.h>
7#include <i2c.h>
8#include <asm/io.h>
9#include <asm/arch/immap_ls102xa.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/fsl_serdes.h>
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +080012#include <asm/arch/ls102xa_devdis.h>
Yao Yuane0f8f542015-12-05 14:59:10 +080013#include <asm/arch/ls102xa_soc.h>
Yao Yuan064f0a12015-03-03 16:35:18 +080014#include <hwconfig.h>
Wang Huanddf89f92014-09-05 13:52:45 +080015#include <mmc.h>
Mingkai Hu5b0df8a2015-10-26 19:47:41 +080016#include <fsl_csu.h>
Wang Huanddf89f92014-09-05 13:52:45 +080017#include <fsl_esdhc.h>
18#include <fsl_ifc.h>
York Sun1006cad2015-04-29 10:35:35 -070019#include <fsl_immap.h>
Wang Huanddf89f92014-09-05 13:52:45 +080020#include <netdev.h>
21#include <fsl_mdio.h>
22#include <tsec.h>
Ruchika Gupta901ae762014-10-15 11:39:06 +053023#include <fsl_sec.h>
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +080024#include <fsl_devdis.h>
Alison Wang948c6092014-12-03 15:00:48 +080025#include <spl.h>
Tang Yuantian8b160bc2015-05-14 17:20:28 +080026#include "../common/sleep.h"
Zhao Qiangf3cc6b72014-09-26 16:25:33 +080027#ifdef CONFIG_U_QE
Qianyu Gongae6a7582016-02-18 13:01:59 +080028#include <fsl_qe.h>
Zhao Qiangf3cc6b72014-09-26 16:25:33 +080029#endif
Aneesh Bansal39d5b3b2016-01-22 16:37:26 +053030#include <fsl_validate.h>
Zhao Qiangf3cc6b72014-09-26 16:25:33 +080031
Wang Huanddf89f92014-09-05 13:52:45 +080032
33DECLARE_GLOBAL_DATA_PTR;
34
35#define VERSION_MASK 0x00FF
36#define BANK_MASK 0x0001
37#define CONFIG_RESET 0x1
38#define INIT_RESET 0x1
39
40#define CPLD_SET_MUX_SERDES 0x20
41#define CPLD_SET_BOOT_BANK 0x40
42
43#define BOOT_FROM_UPPER_BANK 0x0
44#define BOOT_FROM_LOWER_BANK 0x1
45
46#define LANEB_SATA (0x01)
47#define LANEB_SGMII1 (0x02)
48#define LANEC_SGMII1 (0x04)
49#define LANEC_PCIEX1 (0x08)
50#define LANED_PCIEX2 (0x10)
51#define LANED_SGMII2 (0x20)
52
53#define MASK_LANE_B 0x1
54#define MASK_LANE_C 0x2
55#define MASK_LANE_D 0x4
56#define MASK_SGMII 0x8
57
58#define KEEP_STATUS 0x0
59#define NEED_RESET 0x1
60
Yao Yuan064f0a12015-03-03 16:35:18 +080061#define SOFT_MUX_ON_I2C3_IFC 0x2
62#define SOFT_MUX_ON_CAN3_USB2 0x8
63#define SOFT_MUX_ON_QE_LCD 0x10
64
65#define PIN_I2C3_IFC_MUX_I2C3 0x0
66#define PIN_I2C3_IFC_MUX_IFC 0x1
67#define PIN_CAN3_USB2_MUX_USB2 0x0
68#define PIN_CAN3_USB2_MUX_CAN3 0x1
69#define PIN_QE_LCD_MUX_LCD 0x0
70#define PIN_QE_LCD_MUX_QE 0x1
71
Wang Huanddf89f92014-09-05 13:52:45 +080072struct cpld_data {
73 u8 cpld_ver; /* cpld revision */
74 u8 cpld_ver_sub; /* cpld sub revision */
75 u8 pcba_ver; /* pcb revision number */
76 u8 system_rst; /* reset system by cpld */
77 u8 soft_mux_on; /* CPLD override physical switches Enable */
78 u8 cfg_rcw_src1; /* Reset config word 1 */
79 u8 cfg_rcw_src2; /* Reset config word 2 */
80 u8 vbank; /* Flash bank selection Control */
81 u8 gpio; /* GPIO for TWR-ELEV */
82 u8 i2c3_ifc_mux;
83 u8 mux_spi2;
84 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
85 u8 qe_lcd_mux; /* QE and LCD Selection */
86 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
87 u8 global_rst; /* reset with init CPLD reg to default */
88 u8 rev1; /* Reserved */
89 u8 rev2; /* Reserved */
90};
91
Alison Wangdd45cc52015-10-15 17:54:40 +080092#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Tom Rinie982d182018-01-03 09:01:33 -050093static void cpld_show(void)
Wang Huanddf89f92014-09-05 13:52:45 +080094{
95 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
96
97 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
98 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
99 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
100 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
101 in_8(&cpld_data->vbank) & BANK_MASK);
102
103#ifdef CONFIG_DEBUG
104 printf("soft_mux_on =%x\n",
105 in_8(&cpld_data->soft_mux_on));
106 printf("cfg_rcw_src1 =%x\n",
107 in_8(&cpld_data->cfg_rcw_src1));
108 printf("cfg_rcw_src2 =%x\n",
109 in_8(&cpld_data->cfg_rcw_src2));
110 printf("vbank =%x\n",
111 in_8(&cpld_data->vbank));
112 printf("gpio =%x\n",
113 in_8(&cpld_data->gpio));
114 printf("i2c3_ifc_mux =%x\n",
115 in_8(&cpld_data->i2c3_ifc_mux));
116 printf("mux_spi2 =%x\n",
117 in_8(&cpld_data->mux_spi2));
118 printf("can3_usb2_mux =%x\n",
119 in_8(&cpld_data->can3_usb2_mux));
120 printf("qe_lcd_mux =%x\n",
121 in_8(&cpld_data->qe_lcd_mux));
122 printf("serdes_mux =%x\n",
123 in_8(&cpld_data->serdes_mux));
124#endif
125}
Alison Wang2145a372014-12-09 17:38:02 +0800126#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800127
128int checkboard(void)
129{
130 puts("Board: LS1021ATWR\n");
Alison Wangdd45cc52015-10-15 17:54:40 +0800131#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanddf89f92014-09-05 13:52:45 +0800132 cpld_show();
Alison Wang2145a372014-12-09 17:38:02 +0800133#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800134
135 return 0;
136}
137
138void ddrmc_init(void)
139{
140 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
Shengzhou Liu80a12ab2016-09-01 14:50:36 +0800141 u32 temp_sdram_cfg, tmp;
Wang Huanddf89f92014-09-05 13:52:45 +0800142
143 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
144
145 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
146 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
147
148 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
149 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
150 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
151 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
152 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
153 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
154
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800155#ifdef CONFIG_DEEP_SLEEP
156 if (is_warm_boot()) {
157 out_be32(&ddr->sdram_cfg_2,
158 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
159 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
160 out_be32(&ddr->init_ext_addr, (1 << 31));
161
162 /* DRAM VRef will not be trained */
163 out_be32(&ddr->ddr_cdr2,
164 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
165 } else
166#endif
167 {
168 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
169 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
170 }
Wang Huanddf89f92014-09-05 13:52:45 +0800171
172 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
173 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
174
175 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
176
177 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
178
179 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
180 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
181
182 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
Wang Huanddf89f92014-09-05 13:52:45 +0800183
184 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
185 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
186
187 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
Shengzhou Liu80a12ab2016-09-01 14:50:36 +0800188
189 /* DDR erratum A-009942 */
190 tmp = in_be32(&ddr->debug[28]);
191 out_be32(&ddr->debug[28], tmp | 0x0070006f);
192
Wang Huanddf89f92014-09-05 13:52:45 +0800193 udelay(1);
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800194
195#ifdef CONFIG_DEEP_SLEEP
196 if (is_warm_boot()) {
197 /* enter self-refresh */
198 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
199 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
200 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
201
202 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
203 } else
204#endif
205 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
206
207 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
208
209#ifdef CONFIG_DEEP_SLEEP
210 if (is_warm_boot()) {
211 /* exit self-refresh */
212 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
213 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
214 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
215 }
216#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800217}
218
219int dram_init(void)
220{
221#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
222 ddrmc_init();
223#endif
224
Alison Wangd6be97b2019-03-06 14:49:14 +0800225 erratum_a008850_post();
226
Wang Huanddf89f92014-09-05 13:52:45 +0800227 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800228
229#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
230 fsl_dp_resume();
231#endif
232
Wang Huanddf89f92014-09-05 13:52:45 +0800233 return 0;
234}
235
236#ifdef CONFIG_FSL_ESDHC
237struct fsl_esdhc_cfg esdhc_cfg[1] = {
238 {CONFIG_SYS_FSL_ESDHC_ADDR},
239};
240
241int board_mmc_init(bd_t *bis)
242{
243 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
244
245 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
246}
247#endif
248
Wang Huanddf89f92014-09-05 13:52:45 +0800249int board_eth_init(bd_t *bis)
250{
Wang Huanddf89f92014-09-05 13:52:45 +0800251 return pci_eth_init(bis);
252}
Wang Huanddf89f92014-09-05 13:52:45 +0800253
Alison Wangdd45cc52015-10-15 17:54:40 +0800254#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Tom Rinie982d182018-01-03 09:01:33 -0500255static void convert_serdes_mux(int type, int need_reset)
256{
257 char current_serdes;
258 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
259
260 current_serdes = cpld_data->serdes_mux;
261
262 switch (type) {
263 case LANEB_SATA:
264 current_serdes &= ~MASK_LANE_B;
265 break;
266 case LANEB_SGMII1:
267 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
268 break;
269 case LANEC_SGMII1:
270 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
271 break;
272 case LANED_SGMII2:
273 current_serdes |= MASK_LANE_D;
274 break;
275 case LANEC_PCIEX1:
276 current_serdes |= MASK_LANE_C;
277 break;
278 case (LANED_PCIEX2 | LANEC_PCIEX1):
279 current_serdes |= MASK_LANE_C;
280 current_serdes &= ~MASK_LANE_D;
281 break;
282 default:
283 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
284 return;
285 }
286
287 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
288 cpld_data->serdes_mux = current_serdes;
289
290 if (need_reset == 1) {
291 printf("Reset board to enable configuration\n");
292 cpld_data->system_rst = CONFIG_RESET;
293 }
294}
295
Wang Huanddf89f92014-09-05 13:52:45 +0800296int config_serdes_mux(void)
297{
298 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
299 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
300
301 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
302 switch (protocol) {
303 case 0x10:
304 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
305 convert_serdes_mux(LANED_PCIEX2 |
306 LANEC_PCIEX1, KEEP_STATUS);
307 break;
308 case 0x20:
309 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
310 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
311 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
312 break;
313 case 0x30:
314 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
315 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
316 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
317 break;
318 case 0x70:
319 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
320 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
321 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
322 break;
323 }
324
325 return 0;
326}
Alison Wang2145a372014-12-09 17:38:02 +0800327#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800328
Alison Wangdd45cc52015-10-15 17:54:40 +0800329#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Yao Yuan064f0a12015-03-03 16:35:18 +0800330int config_board_mux(void)
331{
332 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
333 int conflict_flag;
334
335 conflict_flag = 0;
336 if (hwconfig("i2c3")) {
337 conflict_flag++;
338 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
339 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
340 }
341
342 if (hwconfig("ifc")) {
343 conflict_flag++;
344 /* some signals can not enable simultaneous*/
345 if (conflict_flag > 1)
346 goto conflict;
347 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
348 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
349 }
350
351 conflict_flag = 0;
352 if (hwconfig("usb2")) {
353 conflict_flag++;
354 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
355 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
356 }
357
358 if (hwconfig("can3")) {
359 conflict_flag++;
360 /* some signals can not enable simultaneous*/
361 if (conflict_flag > 1)
362 goto conflict;
363 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
364 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
365 }
366
367 conflict_flag = 0;
368 if (hwconfig("lcd")) {
369 conflict_flag++;
370 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
371 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
372 }
373
374 if (hwconfig("qe")) {
375 conflict_flag++;
376 /* some signals can not enable simultaneous*/
377 if (conflict_flag > 1)
378 goto conflict;
379 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
380 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
381 }
382
383 return 0;
384
385conflict:
386 printf("WARNING: pin conflict! MUX setting may failed!\n");
387 return 0;
388}
389#endif
390
Wang Huanddf89f92014-09-05 13:52:45 +0800391int board_early_init_f(void)
392{
393 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
394
395#ifdef CONFIG_TSEC_ENET
Claudiu Manoil51b503e2015-08-12 13:29:14 +0300396 /* clear BD & FR bits for BE BD's and frame data */
397 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
Wang Huanddf89f92014-09-05 13:52:45 +0800398 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
Wang Huanddf89f92014-09-05 13:52:45 +0800399#endif
400
401#ifdef CONFIG_FSL_IFC
402 init_early_memctl_regs();
403#endif
404
Yao Yuane0f8f542015-12-05 14:59:10 +0800405 arch_soc_init();
Alison Wangd42fc522015-01-15 17:29:29 +0800406
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800407#if defined(CONFIG_DEEP_SLEEP)
tang yuantianfcefdad2015-09-24 15:52:02 +0800408 if (is_warm_boot()) {
409 timer_init();
410 dram_init();
411 }
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800412#endif
413
Wang Huanddf89f92014-09-05 13:52:45 +0800414 return 0;
415}
416
Alison Wang948c6092014-12-03 15:00:48 +0800417#ifdef CONFIG_SPL_BUILD
418void board_init_f(ulong dummy)
419{
tang yuantianfcefdad2015-09-24 15:52:02 +0800420 void (*second_uboot)(void);
421
Alison Wang948c6092014-12-03 15:00:48 +0800422 /* Clear the BSS */
423 memset(__bss_start, 0, __bss_end - __bss_start);
424
425 get_clocks();
426
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800427#if defined(CONFIG_DEEP_SLEEP)
428 if (is_warm_boot())
429 fsl_dp_disable_console();
430#endif
431
Alison Wang948c6092014-12-03 15:00:48 +0800432 preloader_console_init();
433
Alison Wang28253032018-10-16 16:19:22 +0800434 timer_init();
Alison Wang948c6092014-12-03 15:00:48 +0800435 dram_init();
436
Alison Wang5dec9d72015-07-09 10:50:07 +0800437 /* Allow OCRAM access permission as R/W */
Mingkai Hu5b0df8a2015-10-26 19:47:41 +0800438#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
439 enable_layerscape_ns_access();
Alison Wang5dec9d72015-07-09 10:50:07 +0800440#endif
441
tang yuantianfcefdad2015-09-24 15:52:02 +0800442 /*
443 * if it is woken up from deep sleep, then jump to second
444 * stage uboot and continue executing without recopying
445 * it from SD since it has already been reserved in memeory
446 * in last boot.
447 */
448 if (is_warm_boot()) {
449 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
450 second_uboot();
451 }
452
Alison Wang948c6092014-12-03 15:00:48 +0800453 board_init_r(NULL, 0);
454}
455#endif
456
chenhui zhao08a01d42015-05-15 14:42:30 +0800457#ifdef CONFIG_DEEP_SLEEP
458/* program the regulator (MC34VR500) to support deep sleep */
459void ls1twr_program_regulator(void)
460{
461 unsigned int i2c_bus;
462 u8 i2c_device_id;
463
464#define LS1TWR_I2C_BUS_MC34VR500 1
465#define MC34VR500_ADDR 0x8
466#define MC34VR500_DEVICEID 0x4
467#define MC34VR500_DEVICEID_MASK 0x0f
468
469 i2c_bus = i2c_get_bus_num();
470 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
471 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
472 MC34VR500_DEVICEID_MASK;
473 if (i2c_device_id != MC34VR500_DEVICEID) {
474 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
475 return;
476 }
477
478 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
479 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
480 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
481 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
482 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
483
484 i2c_set_bus_num(i2c_bus);
485}
486#endif
487
Wang Huanddf89f92014-09-05 13:52:45 +0800488int board_init(void)
489{
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +0800490#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
491 erratum_a010315();
492#endif
493
Wang Huanddf89f92014-09-05 13:52:45 +0800494#ifndef CONFIG_SYS_FSL_NO_SERDES
495 fsl_serdes_init();
Alison Wangdd45cc52015-10-15 17:54:40 +0800496#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanddf89f92014-09-05 13:52:45 +0800497 config_serdes_mux();
498#endif
Alison Wang2145a372014-12-09 17:38:02 +0800499#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800500
Alison Wang69364922016-02-05 12:48:17 +0800501 ls102xa_smmu_stream_id_init();
Xiubo Li03d40aa2014-11-21 17:40:59 +0800502
Zhao Qiangf3cc6b72014-09-26 16:25:33 +0800503#ifdef CONFIG_U_QE
504 u_qe_init();
505#endif
506
chenhui zhao08a01d42015-05-15 14:42:30 +0800507#ifdef CONFIG_DEEP_SLEEP
508 ls1twr_program_regulator();
509#endif
Wang Huanddf89f92014-09-05 13:52:45 +0800510 return 0;
511}
512
Sumit Garge2ca9432016-06-14 13:52:40 -0400513#if defined(CONFIG_SPL_BUILD)
514void spl_board_init(void)
515{
516 ls102xa_smmu_stream_id_init();
517}
518#endif
519
tang yuantian9f51db22015-10-16 16:06:05 +0800520#ifdef CONFIG_BOARD_LATE_INIT
521int board_late_init(void)
522{
Aneesh Bansal39d5b3b2016-01-22 16:37:26 +0530523#ifdef CONFIG_CHAIN_OF_TRUST
524 fsl_setenv_chain_of_trust();
525#endif
tang yuantian9f51db22015-10-16 16:06:05 +0800526
527 return 0;
528}
529#endif
530
Ruchika Gupta901ae762014-10-15 11:39:06 +0530531#if defined(CONFIG_MISC_INIT_R)
532int misc_init_r(void)
533{
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +0800534#ifdef CONFIG_FSL_DEVICE_DISABLE
535 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
536#endif
Alison Wangdd45cc52015-10-15 17:54:40 +0800537#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Yao Yuan064f0a12015-03-03 16:35:18 +0800538 config_board_mux();
539#endif
540
Ruchika Gupta901ae762014-10-15 11:39:06 +0530541#ifdef CONFIG_FSL_CAAM
542 return sec_init();
543#endif
544}
545#endif
546
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800547#if defined(CONFIG_DEEP_SLEEP)
548void board_sleep_prepare(void)
549{
Mingkai Hu5b0df8a2015-10-26 19:47:41 +0800550#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
551 enable_layerscape_ns_access();
Tang Yuantian8b160bc2015-05-14 17:20:28 +0800552#endif
553}
554#endif
555
Simon Glass2aec3cc2014-10-23 18:58:47 -0600556int ft_board_setup(void *blob, bd_t *bd)
Wang Huanddf89f92014-09-05 13:52:45 +0800557{
558 ft_cpu_setup(blob, bd);
Simon Glass2aec3cc2014-10-23 18:58:47 -0600559
Minghuan Lian0c535242015-03-12 10:58:48 +0800560#ifdef CONFIG_PCI
561 ft_pci_setup(blob, bd);
Minghuan Liana4d6b612014-10-31 13:43:44 +0800562#endif
563
Simon Glass2aec3cc2014-10-23 18:58:47 -0600564 return 0;
Wang Huanddf89f92014-09-05 13:52:45 +0800565}
566
567u8 flash_read8(void *addr)
568{
569 return __raw_readb(addr + 1);
570}
571
572void flash_write16(u16 val, void *addr)
573{
574 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
575
576 __raw_writew(shftval, addr);
577}
578
579u16 flash_read16(void *addr)
580{
581 u16 val = __raw_readw(addr);
582
583 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
584}
585
Tom Rinie982d182018-01-03 09:01:33 -0500586#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
587 && !defined(CONFIG_SPL_BUILD)
Wang Huanddf89f92014-09-05 13:52:45 +0800588static void convert_flash_bank(char bank)
589{
590 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
591
592 printf("Now switch to boot from flash bank %d.\n", bank);
593 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
594 cpld_data->vbank = bank;
595
596 printf("Reset board to enable configuration.\n");
597 cpld_data->system_rst = CONFIG_RESET;
598}
599
600static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
601 char * const argv[])
602{
603 if (argc != 2)
604 return CMD_RET_USAGE;
605 if (strcmp(argv[1], "0") == 0)
606 convert_flash_bank(BOOT_FROM_UPPER_BANK);
607 else if (strcmp(argv[1], "1") == 0)
608 convert_flash_bank(BOOT_FROM_LOWER_BANK);
609 else
610 return CMD_RET_USAGE;
611
612 return 0;
613}
614
615U_BOOT_CMD(
616 boot_bank, 2, 0, flash_bank_cmd,
617 "Flash bank Selection Control",
618 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
619);
620
621static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
622 char * const argv[])
623{
624 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
625
626 if (argc > 2)
627 return CMD_RET_USAGE;
628 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
629 cpld_data->system_rst = CONFIG_RESET;
630 else if (strcmp(argv[1], "init") == 0)
631 cpld_data->global_rst = INIT_RESET;
632 else
633 return CMD_RET_USAGE;
634
635 return 0;
636}
637
638U_BOOT_CMD(
639 cpld_reset, 2, 0, cpld_reset_cmd,
640 "Reset via CPLD",
641 "conf\n"
642 " -reset with current CPLD configuration\n"
643 "init\n"
644 " -reset and initial CPLD configuration with default value"
645
646);
647
Tom Rinie982d182018-01-03 09:01:33 -0500648static void print_serdes_mux(void)
Wang Huanddf89f92014-09-05 13:52:45 +0800649{
650 char current_serdes;
651 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
652
653 current_serdes = cpld_data->serdes_mux;
654
655 printf("Serdes Lane B: ");
656 if ((current_serdes & MASK_LANE_B) == 0)
657 printf("SATA,\n");
658 else
659 printf("SGMII 1,\n");
660
661 printf("Serdes Lane C: ");
662 if ((current_serdes & MASK_LANE_C) == 0)
663 printf("SGMII 1,\n");
664 else
665 printf("PCIe,\n");
666
667 printf("Serdes Lane D: ");
668 if ((current_serdes & MASK_LANE_D) == 0)
669 printf("PCIe,\n");
670 else
671 printf("SGMII 2,\n");
672
673 printf("SGMII 1 is on lane ");
674 if ((current_serdes & MASK_SGMII) == 0)
675 printf("C.\n");
676 else
677 printf("B.\n");
678}
679
680static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
681 char * const argv[])
682{
683 if (argc != 2)
684 return CMD_RET_USAGE;
685 if (strcmp(argv[1], "sata") == 0) {
686 printf("Set serdes lane B to SATA.\n");
687 convert_serdes_mux(LANEB_SATA, NEED_RESET);
688 } else if (strcmp(argv[1], "sgmii1b") == 0) {
689 printf("Set serdes lane B to SGMII 1.\n");
690 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
691 } else if (strcmp(argv[1], "sgmii1c") == 0) {
692 printf("Set serdes lane C to SGMII 1.\n");
693 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
694 } else if (strcmp(argv[1], "sgmii2") == 0) {
695 printf("Set serdes lane D to SGMII 2.\n");
696 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
697 } else if (strcmp(argv[1], "pciex1") == 0) {
698 printf("Set serdes lane C to PCIe X1.\n");
699 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
700 } else if (strcmp(argv[1], "pciex2") == 0) {
701 printf("Set serdes lane C & lane D to PCIe X2.\n");
702 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
703 } else if (strcmp(argv[1], "show") == 0) {
704 print_serdes_mux();
705 } else {
706 return CMD_RET_USAGE;
707 }
708
709 return 0;
710}
711
712U_BOOT_CMD(
713 lane_bank, 2, 0, serdes_mux_cmd,
714 "Multiplexed function setting for SerDes Lanes",
715 "sata\n"
716 " -change lane B to sata\n"
717 "lane_bank sgmii1b\n"
718 " -change lane B to SGMII1\n"
719 "lane_bank sgmii1c\n"
720 " -change lane C to SGMII1\n"
721 "lane_bank sgmii2\n"
722 " -change lane D to SGMII2\n"
723 "lane_bank pciex1\n"
724 " -change lane C to PCIeX1\n"
725 "lane_bank pciex2\n"
726 " -change lane C & lane D to PCIeX2\n"
727 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
728);
Alison Wang2145a372014-12-09 17:38:02 +0800729#endif