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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumar227b4bc2017-08-31 16:12:54 +05302/*
Pramod Kumara0531822018-10-12 14:04:27 +00003 * Copyright 2017-2018 NXP
Ashish Kumar227b4bc2017-08-31 16:12:54 +05304 */
5
6#ifndef __LS1088_COMMON_H
7#define __LS1088_COMMON_H
8
Sumit Garg08da8b22018-01-06 09:04:24 +05309/* SPL build */
10#ifdef CONFIG_SPL_BUILD
11#define SPL_NO_BOARDINFO
12#define SPL_NO_QIXIS
13#define SPL_NO_PCI
14#define SPL_NO_ENV
15#define SPL_NO_RTC
16#define SPL_NO_USB
17#define SPL_NO_SATA
18#define SPL_NO_QSPI
19#define SPL_NO_IFC
Sumit Garg08da8b22018-01-06 09:04:24 +053020#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +053021
Ashish Kumar227b4bc2017-08-31 16:12:54 +053022#include <asm/arch/stream_id_lsch3.h>
23#include <asm/arch/config.h>
24#include <asm/arch/soc.h>
25
Pramod Kumara0531822018-10-12 14:04:27 +000026#define LS1088ARDB_PB_BOARD 0x4A
Ashish Kumar227b4bc2017-08-31 16:12:54 +053027/* Link Definitions */
Ashish Kumar227b4bc2017-08-31 16:12:54 +053028
29/* Link Definitions */
Tom Rini376b88a2022-10-28 20:27:13 -040030#define CFG_SYS_FSL_QSPI_BASE 0x20000000
Ashish Kumar227b4bc2017-08-31 16:12:54 +053031
Tom Rini6a5dccc2022-11-16 13:10:41 -050032#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
Tom Rini376b88a2022-10-28 20:27:13 -040033#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
Tom Rini6a5dccc2022-11-16 13:10:41 -050034#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
35#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
Ashish Kumar227b4bc2017-08-31 16:12:54 +053036/*
37 * SMP Definitinos
38 */
Michael Wallef056e0f2020-06-01 21:53:26 +020039#define CPU_RELEASE_ADDR secondary_boot_addr
Ashish Kumar227b4bc2017-08-31 16:12:54 +053040
Biwen Lia5c9e122021-02-05 19:01:58 +080041/* GPIO */
Biwen Lia5c9e122021-02-05 19:01:58 +080042
Ashish Kumar227b4bc2017-08-31 16:12:54 +053043/* I2C */
Chuanhua Han8a898462019-07-23 18:43:11 +080044
Ashish Kumar227b4bc2017-08-31 16:12:54 +053045
46/* Serial Port */
Tom Rinidf6a2152022-11-16 13:10:28 -050047#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
Ashish Kumar227b4bc2017-08-31 16:12:54 +053048
Ashish Kumar227b4bc2017-08-31 16:12:54 +053049/*
50 * During booting, IFC is mapped at the region of 0x30000000.
51 * But this region is limited to 256MB. To accommodate NOR, promjet
52 * and FPGA. This region is divided as below:
53 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
54 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
55 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
56 *
57 * To accommodate bigger NOR flash and other devices, we will map IFC
58 * chip selects to as below:
59 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
60 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
61 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
62 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
63 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
64 *
65 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
Tom Rini6a5dccc2022-11-16 13:10:41 -050066 * CFG_SYS_FLASH_BASE has the final address (core view)
67 * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
68 * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
Simon Glass72cc5382022-10-20 18:22:39 -060069 * CONFIG_TEXT_BASE is linked to 0x30000000 for booting
Ashish Kumar227b4bc2017-08-31 16:12:54 +053070 */
71
Tom Rini6a5dccc2022-11-16 13:10:41 -050072#define CFG_SYS_FLASH_BASE 0x580000000ULL
73#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
74#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
Ashish Kumar227b4bc2017-08-31 16:12:54 +053075
Tom Rini6a5dccc2022-11-16 13:10:41 -050076#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
77#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
Ashish Kumar227b4bc2017-08-31 16:12:54 +053078
79#ifndef __ASSEMBLY__
80unsigned long long get_qixis_addr(void);
81#endif
82
83#define QIXIS_BASE get_qixis_addr()
84#define QIXIS_BASE_PHYS 0x20000000
85#define QIXIS_BASE_PHYS_EARLY 0xC000000
86
87
Tom Rinib4213492022-11-12 17:36:51 -050088#define CFG_SYS_NAND_BASE 0x530000000ULL
89#define CFG_SYS_NAND_BASE_PHYS 0x30000000
Ashish Kumar227b4bc2017-08-31 16:12:54 +053090
91
92/* MC firmware */
93/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
Tom Rini6a5dccc2022-11-16 13:10:41 -050094#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
95#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
96#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
97#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
98#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
99#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
Bogdan Purcareata33ba9392017-10-05 06:56:53 +0000100
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530101/*
102 * Carve out a DDR region which will not be used by u-boot/Linux
103 *
104 * It will be used by MC and Debug Server. The MC region must be
105 * 512MB aligned, so the min size to hide is 512MB.
106 */
107
108#if defined(CONFIG_FSL_MC_ENET)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500109#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530110#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530111
112/* Miscellaneous configurable options */
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530113
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530114/* Physical Memory Map */
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530115
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530116#define HWCONFIG_BUFFER_SIZE 128
117
Sumit Garg08da8b22018-01-06 09:04:24 +0530118#ifndef SPL_NO_ENV
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530119/* Initial environment variables */
Tom Rinic9edebe2022-12-04 10:03:50 -0500120#define CFG_EXTRA_ENV_SETTINGS \
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530121 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
122 "loadaddr=0x80100000\0" \
123 "kernel_addr=0x100000\0" \
124 "ramdisk_addr=0x800000\0" \
125 "ramdisk_size=0x2000000\0" \
126 "fdt_high=0xa0000000\0" \
127 "initrd_high=0xffffffffffffffff\0" \
128 "kernel_start=0x581000000\0" \
129 "kernel_load=0xa0000000\0" \
130 "kernel_size=0x2800000\0" \
131 "console=ttyAMA0,38400n8\0" \
132 "mcinitcmd=fsl_mc start mc 0x580a00000" \
133 " 0x580e00000 \0"
Sumit Garg08da8b22018-01-06 09:04:24 +0530134#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530135
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530136#endif /* __LS1088_COMMON_H */