Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor |
Camelia Groza | a1c4699 | 2022-07-28 17:28:11 +0300 | [diff] [blame] | 4 | * Copyright 2022 NXP |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __LS1043ARDB_H__ |
| 8 | #define __LS1043ARDB_H__ |
| 9 | |
| 10 | #include "ls1043a_common.h" |
| 11 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 12 | /* |
| 13 | * NOR Flash Definitions |
| 14 | */ |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 15 | #define CFG_SYS_NOR_CSPR_EXT (0x0) |
| 16 | #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 17 | #define CFG_SYS_NOR_CSPR \ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 18 | (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 19 | CSPR_PORT_SIZE_16 | \ |
| 20 | CSPR_MSEL_NOR | \ |
| 21 | CSPR_V) |
| 22 | |
| 23 | /* NOR Flash Timing Params */ |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 24 | #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 25 | CSOR_NOR_TRHZ_80) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 26 | #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 27 | FTIM0_NOR_TEADC(0x1) | \ |
| 28 | FTIM0_NOR_TAVDS(0x0) | \ |
| 29 | FTIM0_NOR_TEAHC(0xc)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 30 | #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 31 | FTIM1_NOR_TRAD_NOR(0xb) | \ |
| 32 | FTIM1_NOR_TSEQRAD_NOR(0x9)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 33 | #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 34 | FTIM2_NOR_TCH(0x4) | \ |
| 35 | FTIM2_NOR_TWPH(0x8) | \ |
| 36 | FTIM2_NOR_TWP(0x10)) |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 37 | #define CFG_SYS_NOR_FTIM3 0 |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 38 | #define CFG_SYS_IFC_CCR 0x01000000 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 39 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 40 | #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 41 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 42 | #define CFG_SYS_WRITE_SWAPPED_DATA |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * NAND Flash Definitions |
| 46 | */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 47 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 48 | #define CFG_SYS_NAND_BASE 0x7e800000 |
| 49 | #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 50 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 51 | #define CFG_SYS_NAND_CSPR_EXT (0x0) |
| 52 | #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 53 | | CSPR_PORT_SIZE_8 \ |
| 54 | | CSPR_MSEL_NAND \ |
| 55 | | CSPR_V) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 56 | #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 57 | #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 58 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 59 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 60 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| 61 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| 62 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ |
| 63 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| 64 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 65 | #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 66 | FTIM0_NAND_TWP(0x18) | \ |
| 67 | FTIM0_NAND_TWCHT(0x7) | \ |
| 68 | FTIM0_NAND_TWH(0xa)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 69 | #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 70 | FTIM1_NAND_TWBE(0x39) | \ |
| 71 | FTIM1_NAND_TRR(0xe) | \ |
| 72 | FTIM1_NAND_TRP(0x18)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 73 | #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 74 | FTIM2_NAND_TREH(0xa) | \ |
| 75 | FTIM2_NAND_TWHRE(0x1e)) |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 76 | #define CFG_SYS_NAND_FTIM3 0x0 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 77 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 78 | #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 79 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 80 | #ifdef CONFIG_NAND_BOOT |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 81 | #define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 82 | #endif |
| 83 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 84 | /* |
| 85 | * CPLD |
| 86 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 87 | #define CFG_SYS_CPLD_BASE 0x7fb00000 |
| 88 | #define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 89 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 90 | #define CFG_SYS_CPLD_CSPR_EXT (0x0) |
| 91 | #define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 92 | CSPR_PORT_SIZE_8 | \ |
| 93 | CSPR_MSEL_GPCM | \ |
| 94 | CSPR_V) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 95 | #define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
| 96 | #define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 97 | CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| 98 | CSOR_NOR_TRHZ_80) |
| 99 | |
| 100 | /* CPLD Timing parameters for IFC GPCM */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 101 | #define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 102 | FTIM0_GPCM_TEADC(0xf) | \ |
| 103 | FTIM0_GPCM_TEAHC(0xf)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 104 | #define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 105 | FTIM1_GPCM_TRAD(0x3f)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 106 | #define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 107 | FTIM2_GPCM_TCH(0xf) | \ |
| 108 | FTIM2_GPCM_TWP(0xff)) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 109 | #define CFG_SYS_CPLD_FTIM3 0x0 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 110 | |
| 111 | /* IFC Timing Params */ |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 112 | #ifdef CONFIG_TFABOOT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 113 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT |
| 114 | #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR |
| 115 | #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK |
| 116 | #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR |
| 117 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 |
| 118 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 |
| 119 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 |
| 120 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 121 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 122 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT |
| 123 | #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR |
| 124 | #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK |
| 125 | #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR |
| 126 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 |
| 127 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 |
| 128 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 |
| 129 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 130 | #else |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 131 | #ifdef CONFIG_NAND_BOOT |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 132 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT |
| 133 | #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR |
| 134 | #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK |
| 135 | #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR |
| 136 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 |
| 137 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 |
| 138 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 |
| 139 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 140 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 141 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT |
| 142 | #define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR |
| 143 | #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK |
| 144 | #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR |
| 145 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 |
| 146 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 |
| 147 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 |
| 148 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 149 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 150 | #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT |
| 151 | #define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR |
| 152 | #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK |
| 153 | #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR |
| 154 | #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 |
| 155 | #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 |
| 156 | #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 |
| 157 | #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 158 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 159 | #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT |
| 160 | #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR |
| 161 | #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK |
| 162 | #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR |
| 163 | #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 |
| 164 | #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 |
| 165 | #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 |
| 166 | #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 167 | #endif |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 168 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 169 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 170 | #define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT |
| 171 | #define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR |
| 172 | #define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK |
| 173 | #define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR |
| 174 | #define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 |
| 175 | #define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 |
| 176 | #define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 |
| 177 | #define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 178 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 179 | /* |
| 180 | * Environment |
| 181 | */ |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 182 | |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 183 | /* FMan */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 184 | #ifndef SPL_NO_FMAN |
York Sun | 5f0580c | 2017-04-25 08:39:52 -0700 | [diff] [blame] | 185 | #define AQR105_IRQ_MASK 0x40000000 |
| 186 | |
York Sun | 5f0580c | 2017-04-25 08:39:52 -0700 | [diff] [blame] | 187 | #ifdef CONFIG_SYS_DPAA_FMAN |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 188 | #define RGMII_PHY1_ADDR 0x1 |
| 189 | #define RGMII_PHY2_ADDR 0x2 |
| 190 | |
| 191 | #define QSGMII_PORT1_PHY_ADDR 0x4 |
| 192 | #define QSGMII_PORT2_PHY_ADDR 0x5 |
| 193 | #define QSGMII_PORT3_PHY_ADDR 0x6 |
| 194 | #define QSGMII_PORT4_PHY_ADDR 0x7 |
| 195 | |
Camelia Groza | a1c4699 | 2022-07-28 17:28:11 +0300 | [diff] [blame] | 196 | /* The AQR PHY model and MDIO address differ between board revisions */ |
| 197 | #define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */ |
| 198 | #define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */ |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 199 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 200 | #endif |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 201 | |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 202 | /* SATA */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 203 | #ifndef SPL_NO_SATA |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 204 | #define SCSI_VEND_ID 0x1b4b |
| 205 | #define SCSI_DEV_ID 0x9170 |
Tom Rini | 6173acb | 2022-12-04 10:13:44 -0500 | [diff] [blame] | 206 | #define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 207 | #endif |
Po Liu | 2271aa1 | 2016-05-18 10:09:38 +0800 | [diff] [blame] | 208 | |
Aneesh Bansal | b3e9820 | 2015-12-08 13:54:29 +0530 | [diff] [blame] | 209 | #include <asm/fsl_secure_boot.h> |
| 210 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 211 | #endif /* __LS1043ARDB_H__ */ |