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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hueee86ff2015-10-26 19:47:52 +08002/*
3 * Copyright 2015 Freescale Semiconductor
Camelia Grozaa1c46992022-07-28 17:28:11 +03004 * Copyright 2022 NXP
Mingkai Hueee86ff2015-10-26 19:47:52 +08005 */
6
7#ifndef __LS1043ARDB_H__
8#define __LS1043ARDB_H__
9
10#include "ls1043a_common.h"
11
Mingkai Hueee86ff2015-10-26 19:47:52 +080012/*
13 * NOR Flash Definitions
14 */
Tom Rini7b577ba2022-11-16 13:10:25 -050015#define CFG_SYS_NOR_CSPR_EXT (0x0)
16#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
17#define CFG_SYS_NOR_CSPR \
Tom Rini6a5dccc2022-11-16 13:10:41 -050018 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080019 CSPR_PORT_SIZE_16 | \
20 CSPR_MSEL_NOR | \
21 CSPR_V)
22
23/* NOR Flash Timing Params */
Tom Rini7b577ba2022-11-16 13:10:25 -050024#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080025 CSOR_NOR_TRHZ_80)
Tom Rini7b577ba2022-11-16 13:10:25 -050026#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080027 FTIM0_NOR_TEADC(0x1) | \
28 FTIM0_NOR_TAVDS(0x0) | \
29 FTIM0_NOR_TEAHC(0xc))
Tom Rini7b577ba2022-11-16 13:10:25 -050030#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080031 FTIM1_NOR_TRAD_NOR(0xb) | \
32 FTIM1_NOR_TSEQRAD_NOR(0x9))
Tom Rini7b577ba2022-11-16 13:10:25 -050033#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080034 FTIM2_NOR_TCH(0x4) | \
35 FTIM2_NOR_TWPH(0x8) | \
36 FTIM2_NOR_TWP(0x10))
Tom Rini7b577ba2022-11-16 13:10:25 -050037#define CFG_SYS_NOR_FTIM3 0
Tom Rini6a5dccc2022-11-16 13:10:41 -050038#define CFG_SYS_IFC_CCR 0x01000000
Mingkai Hueee86ff2015-10-26 19:47:52 +080039
Tom Rini6a5dccc2022-11-16 13:10:41 -050040#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
Mingkai Hueee86ff2015-10-26 19:47:52 +080041
Tom Rini6a5dccc2022-11-16 13:10:41 -050042#define CFG_SYS_WRITE_SWAPPED_DATA
Mingkai Hueee86ff2015-10-26 19:47:52 +080043
44/*
45 * NAND Flash Definitions
46 */
Mingkai Hueee86ff2015-10-26 19:47:52 +080047
Tom Rinib4213492022-11-12 17:36:51 -050048#define CFG_SYS_NAND_BASE 0x7e800000
49#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
Mingkai Hueee86ff2015-10-26 19:47:52 +080050
Tom Rinib4213492022-11-12 17:36:51 -050051#define CFG_SYS_NAND_CSPR_EXT (0x0)
52#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
Mingkai Hueee86ff2015-10-26 19:47:52 +080053 | CSPR_PORT_SIZE_8 \
54 | CSPR_MSEL_NAND \
55 | CSPR_V)
Tom Rinib4213492022-11-12 17:36:51 -050056#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
57#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
Mingkai Hueee86ff2015-10-26 19:47:52 +080058 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
59 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
60 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
61 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
62 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
63 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
64
Tom Rinib4213492022-11-12 17:36:51 -050065#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080066 FTIM0_NAND_TWP(0x18) | \
67 FTIM0_NAND_TWCHT(0x7) | \
68 FTIM0_NAND_TWH(0xa))
Tom Rinib4213492022-11-12 17:36:51 -050069#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080070 FTIM1_NAND_TWBE(0x39) | \
71 FTIM1_NAND_TRR(0xe) | \
72 FTIM1_NAND_TRP(0x18))
Tom Rinib4213492022-11-12 17:36:51 -050073#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080074 FTIM2_NAND_TREH(0xa) | \
75 FTIM2_NAND_TWHRE(0x1e))
Tom Rinib4213492022-11-12 17:36:51 -050076#define CFG_SYS_NAND_FTIM3 0x0
Mingkai Hueee86ff2015-10-26 19:47:52 +080077
Tom Rinib4213492022-11-12 17:36:51 -050078#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
Mingkai Hueee86ff2015-10-26 19:47:52 +080079
Gong Qianyu8168a0f2015-10-26 19:47:53 +080080#ifdef CONFIG_NAND_BOOT
Tom Rinib4213492022-11-12 17:36:51 -050081#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
Gong Qianyu8168a0f2015-10-26 19:47:53 +080082#endif
83
Mingkai Hueee86ff2015-10-26 19:47:52 +080084/*
85 * CPLD
86 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050087#define CFG_SYS_CPLD_BASE 0x7fb00000
88#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
Mingkai Hueee86ff2015-10-26 19:47:52 +080089
Tom Rini6a5dccc2022-11-16 13:10:41 -050090#define CFG_SYS_CPLD_CSPR_EXT (0x0)
91#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080092 CSPR_PORT_SIZE_8 | \
93 CSPR_MSEL_GPCM | \
94 CSPR_V)
Tom Rini6a5dccc2022-11-16 13:10:41 -050095#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
96#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +080097 CSOR_NOR_NOR_MODE_AVD_NOR | \
98 CSOR_NOR_TRHZ_80)
99
100/* CPLD Timing parameters for IFC GPCM */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500101#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +0800102 FTIM0_GPCM_TEADC(0xf) | \
103 FTIM0_GPCM_TEAHC(0xf))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500104#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +0800105 FTIM1_GPCM_TRAD(0x3f))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500106#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
Mingkai Hueee86ff2015-10-26 19:47:52 +0800107 FTIM2_GPCM_TCH(0xf) | \
108 FTIM2_GPCM_TWP(0xff))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500109#define CFG_SYS_CPLD_FTIM3 0x0
Mingkai Hueee86ff2015-10-26 19:47:52 +0800110
111/* IFC Timing Params */
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000112#ifdef CONFIG_TFABOOT
Tom Rini6a5dccc2022-11-16 13:10:41 -0500113#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
114#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
115#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
116#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
117#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
118#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
119#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
120#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000121
Tom Rini6a5dccc2022-11-16 13:10:41 -0500122#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
123#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
124#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
125#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
126#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
127#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
128#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
129#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000130#else
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800131#ifdef CONFIG_NAND_BOOT
Tom Rini6a5dccc2022-11-16 13:10:41 -0500132#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
133#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
134#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
135#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
136#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
137#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
138#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
139#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800140
Tom Rini6a5dccc2022-11-16 13:10:41 -0500141#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
142#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
143#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
144#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
145#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
146#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
147#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
148#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800149#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500150#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
151#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
152#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
153#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
154#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
155#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
156#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
157#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
Mingkai Hueee86ff2015-10-26 19:47:52 +0800158
Tom Rini6a5dccc2022-11-16 13:10:41 -0500159#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
160#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
161#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
162#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
163#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
164#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
165#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
166#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800167#endif
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000168#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800169
Tom Rini6a5dccc2022-11-16 13:10:41 -0500170#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT
171#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR
172#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK
173#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR
174#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0
175#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1
176#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2
177#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
Mingkai Hueee86ff2015-10-26 19:47:52 +0800178
Mingkai Hueee86ff2015-10-26 19:47:52 +0800179/*
180 * Environment
181 */
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800182
Shaohui Xie04643262015-10-26 19:47:54 +0800183/* FMan */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530184#ifndef SPL_NO_FMAN
York Sun5f0580c2017-04-25 08:39:52 -0700185#define AQR105_IRQ_MASK 0x40000000
186
York Sun5f0580c2017-04-25 08:39:52 -0700187#ifdef CONFIG_SYS_DPAA_FMAN
Shaohui Xie04643262015-10-26 19:47:54 +0800188#define RGMII_PHY1_ADDR 0x1
189#define RGMII_PHY2_ADDR 0x2
190
191#define QSGMII_PORT1_PHY_ADDR 0x4
192#define QSGMII_PORT2_PHY_ADDR 0x5
193#define QSGMII_PORT3_PHY_ADDR 0x6
194#define QSGMII_PORT4_PHY_ADDR 0x7
195
Camelia Grozaa1c46992022-07-28 17:28:11 +0300196/* The AQR PHY model and MDIO address differ between board revisions */
197#define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */
198#define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */
Shaohui Xie04643262015-10-26 19:47:54 +0800199#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530200#endif
Shaohui Xie04643262015-10-26 19:47:54 +0800201
Po Liu2271aa12016-05-18 10:09:38 +0800202/* SATA */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530203#ifndef SPL_NO_SATA
Po Liu2271aa12016-05-18 10:09:38 +0800204#define SCSI_VEND_ID 0x1b4b
205#define SCSI_DEV_ID 0x9170
Tom Rini6173acb2022-12-04 10:13:44 -0500206#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
Sumit Garg2a2857b2017-03-30 09:52:38 +0530207#endif
Po Liu2271aa12016-05-18 10:09:38 +0800208
Aneesh Bansalb3e98202015-12-08 13:54:29 +0530209#include <asm/fsl_secure_boot.h>
210
Mingkai Hueee86ff2015-10-26 19:47:52 +0800211#endif /* __LS1043ARDB_H__ */