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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop0bf5cad2008-05-08 18:52:25 +02002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9RLEK board.
Stelian Pop0bf5cad2008-05-08 18:52:25 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Xu, Hong0c0fb212011-08-01 03:56:53 +000013#include <asm/hardware.h>
14
Stelian Pop0bf5cad2008-05-08 18:52:25 +020015/* ARM asynchronous clock */
Tom Rini6a5dccc2022-11-16 13:10:41 -050016#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
17#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020018
Stelian Pop0bf5cad2008-05-08 18:52:25 +020019/* SDRAM */
Tom Rinibb4dd962022-11-16 13:10:37 -050020#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
21#define CFG_SYS_SDRAM_SIZE 0x04000000
Xu, Hong0c0fb212011-08-01 03:56:53 +000022
Tom Rini6a5dccc2022-11-16 13:10:41 -050023#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
24#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
Stelian Pop0bf5cad2008-05-08 18:52:25 +020025
Stelian Pop0bf5cad2008-05-08 18:52:25 +020026/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010027#ifdef CONFIG_CMD_NAND
Tom Rinib4213492022-11-12 17:36:51 -050028#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010029/* our ALE is AD21 */
Tom Rinib4213492022-11-12 17:36:51 -050030#define CFG_SYS_NAND_MASK_ALE (1 << 21)
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010031/* our CLE is AD22 */
Tom Rinib4213492022-11-12 17:36:51 -050032#define CFG_SYS_NAND_MASK_CLE (1 << 22)
33#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
34#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +020035
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010036#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +020037
Stelian Pop0bf5cad2008-05-08 18:52:25 +020038#endif