Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2012-2016 Freescale Semiconductor, Inc. |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 7 | #include <log.h> |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 8 | #include <asm/fsl_pamu.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 9 | #include <asm/global_data.h> |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 10 | |
| 11 | DECLARE_GLOBAL_DATA_PTR; |
| 12 | |
| 13 | void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) |
| 14 | { |
| 15 | int i = 0; |
| 16 | int j; |
| 17 | |
| 18 | tbl->start_addr[i] = |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 19 | (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); |
Tom Rini | bc9d46b | 2022-12-04 10:04:50 -0500 | [diff] [blame] | 20 | tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED)); |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 21 | tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; |
| 22 | |
| 23 | i++; |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 24 | #ifdef CFG_SYS_FLASH_BASE_PHYS |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 25 | tbl->start_addr[i] = |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 26 | (uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS); |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 27 | tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ |
| 28 | tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; |
| 29 | |
| 30 | i++; |
| 31 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 32 | #if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) |
Sumit Garg | f6d96cb | 2016-07-14 12:27:51 -0400 | [diff] [blame] | 33 | tbl->start_addr[i] = |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 34 | (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); |
Sumit Garg | f6d96cb | 2016-07-14 12:27:51 -0400 | [diff] [blame] | 35 | tbl->size[i] = 256 * 1024; /* 256K CPC flash */ |
| 36 | tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; |
| 37 | |
| 38 | i++; |
| 39 | #endif |
Aneesh Bansal | 4b636c3 | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 40 | debug("PAMU address\t\t\tsize\n"); |
| 41 | for (j = 0; j < i ; j++) |
| 42 | debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); |
| 43 | |
| 44 | *num_entries = i; |
| 45 | } |
| 46 | |
| 47 | int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s) |
| 48 | { |
| 49 | struct pamu_addr_tbl tbl; |
| 50 | int num_entries = 0; |
| 51 | int ret = 0; |
| 52 | |
| 53 | construct_pamu_addr_table(&tbl, &num_entries); |
| 54 | |
| 55 | ret = config_pamu(&tbl, num_entries, liodn_ns); |
| 56 | if (ret) |
| 57 | return ret; |
| 58 | |
| 59 | ret = config_pamu(&tbl, num_entries, liodn_s); |
| 60 | if (ret) |
| 61 | return ret; |
| 62 | |
| 63 | return ret; |
| 64 | } |