blob: a13afad093ada164ed5554145762590bc29e17d7 [file] [log] [blame]
Angelo Dureghelloc6164c92019-03-13 21:46:41 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
4 */
5
6/ {
7 compatible = "fsl,mcf5301x";
8
9 aliases {
10 serial0 = &uart0;
11 spi0 = &dspi0;
Angelo Durgehelloc6e17f92019-11-15 23:54:12 +010012 fec0 = &fec0;
13 fec1 = &fec1;
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010014 };
15
16 soc {
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 uart0: uart@fc060000 {
22 compatible = "fsl,mcf-uart";
23 reg = <0xfc060000 0x40>;
24 status = "disabled";
25 };
26
27 uart1: uart@fc064000 {
28 compatible = "fsl,mcf-uart";
29 reg = <0xfc064000 0x40>;
30 status = "disabled";
31 };
32
33 uart2: uart@fc068000 {
34 compatible = "fsl,mcf-uart";
35 reg = <0xfc068000 0x40>;
36 status = "disabled";
37 };
38
39 dspi0: dspi@fc05c000 {
40 compatible = "fsl,mcf-dspi";
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0xfc05c000 0x100>;
44 spi-max-frequency = <50000000>;
45 num-cs = <4>;
46 spi-mode = <0>;
47 status = "disabled";
48 };
Angelo Durgehelloc6e17f92019-11-15 23:54:12 +010049
50 fec0: ethernet@fc030000 {
51 compatible = "fsl,mcf-fec";
52 reg = <0xfc030000 0x200>;
53 mii-base = <0>;
54 max-speed = <100>;
55 phy-addr = <(-1)>;
56 timeout-loop = <50000>;
57 status = "disabled";
58 };
59
60 fec1: ethernet@fc034000 {
61 compatible = "fsl,mcf-fec";
62 reg = <0xfc034000 0x800>;
63 mii-base = <1>;
64 max-speed = <100>;
65 timeout-loop = <50000>;
66 status = "disabled";
67 };
Angelo Dureghellod768df12023-04-05 00:59:27 +020068
69 i2c0: i2c@0xfc058000 {
70 compatible = "fsl-i2c";
71 #address-cells=<1>;
72 #size-cells=<0>;
73 cell-index = <0>;
74 reg = <0xfc058000 0x100>;
75 clock-frequency = <100000>;
76 status = "disabled";
77 };
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010078 };
79};