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Reinhard Meyerc718a562010-08-13 10:31:06 +02001/*
2 * Copyright (C) 2010
3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
5 *
6 * Original Driver:
7 * Copyright (C) 2004-2006 Atmel Corporation
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Reinhard Meyerc718a562010-08-13 10:31:06 +020010 */
11
12#include <common.h>
13#include <mmc.h>
14#include <part.h>
15#include <malloc.h>
16#include <asm/io.h>
17#include <asm/errno.h>
18#include <asm/byteorder.h>
19#include <asm/arch/clk.h>
Reinhard Meyer7f619cb2010-11-03 16:32:56 +010020#include <asm/arch/hardware.h>
Reinhard Meyerc718a562010-08-13 10:31:06 +020021#include "atmel_mci.h"
22
23#ifndef CONFIG_SYS_MMC_CLK_OD
24# define CONFIG_SYS_MMC_CLK_OD 150000
25#endif
26
27#define MMC_DEFAULT_BLKLEN 512
28
29#if defined(CONFIG_ATMEL_MCI_PORTB)
30# define MCI_BUS 1
31#else
32# define MCI_BUS 0
33#endif
34
35static int initialized = 0;
36
Bo Shen644b4762013-04-26 00:27:06 +000037/* Read Atmel MCI IP version */
38static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
39{
40 return readl(&mci->version) & 0x00000fff;
41}
42
Reinhard Meyerc718a562010-08-13 10:31:06 +020043/*
44 * Print command and status:
45 *
46 * - always when DEBUG is defined
47 * - on command errors
48 */
49static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
50{
51 printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
52 cmdr, cmdr&0x3F, arg, status, msg);
53}
54
55/* Setup for MCI Clock and Block Size */
56static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
57{
Pantelis Antoniou2c850462014-03-11 19:34:20 +020058 atmel_mci_t *mci = mmc->priv;
Reinhard Meyerc718a562010-08-13 10:31:06 +020059 u32 bus_hz = get_mci_clk_rate();
60 u32 clkdiv = 255;
61
62 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
63 bus_hz, hz, blklen);
64 if (hz > 0) {
65 /* find lowest clkdiv yielding a rate <= than requested */
66 for (clkdiv=0; clkdiv<255; clkdiv++) {
67 if ((bus_hz / (clkdiv+1) / 2) <= hz)
68 break;
69 }
70 }
71 printf("mci: setting clock %u Hz, block size %u\n",
72 (bus_hz / (clkdiv+1)) / 2, blklen);
73
74 blklen &= 0xfffc;
75 /* On some platforms RDPROOF and WRPROOF are ignored */
76 writel((MMCI_BF(CLKDIV, clkdiv)
77 | MMCI_BF(BLKLEN, blklen)
78 | MMCI_BIT(RDPROOF)
79 | MMCI_BIT(WRPROOF)), &mci->mr);
Wu, Joshd1e486b2012-09-13 22:22:04 +000080 /*
81 * On some new platforms BLKLEN in mci->mr is ignored.
82 * Should use the BLKLEN in the block register.
83 */
84 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
Reinhard Meyerc718a562010-08-13 10:31:06 +020085 initialized = 1;
86}
87
88/* Return the CMDR with flags for a given command and data packet */
89static u32 mci_encode_cmd(
90 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
91{
92 u32 cmdr = 0;
93
94 /* Default Flags for Errors */
95 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
96 MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
97
98 /* Default Flags for the Command */
99 cmdr |= MMCI_BIT(MAXLAT);
100
101 if (data) {
102 cmdr |= MMCI_BF(TRCMD, 1);
103 if (data->blocks > 1)
104 cmdr |= MMCI_BF(TRTYP, 1);
105 if (data->flags & MMC_DATA_READ)
106 cmdr |= MMCI_BIT(TRDIR);
107 }
108
109 if (cmd->resp_type & MMC_RSP_CRC)
110 *error_flags |= MMCI_BIT(RCRCE);
111 if (cmd->resp_type & MMC_RSP_136)
112 cmdr |= MMCI_BF(RSPTYP, 2);
113 else if (cmd->resp_type & MMC_RSP_BUSY)
114 cmdr |= MMCI_BF(RSPTYP, 3);
115 else if (cmd->resp_type & MMC_RSP_PRESENT)
116 cmdr |= MMCI_BF(RSPTYP, 1);
117
118 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
119}
120
121/* Entered into function pointer in mci_send_cmd */
122static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
123{
124 u32 status;
125
126 do {
127 status = readl(&mci->sr);
128 if (status & (error_flags | MMCI_BIT(OVRE)))
129 goto io_fail;
130 } while (!(status & MMCI_BIT(RXRDY)));
131
132 if (status & MMCI_BIT(RXRDY)) {
133 *data = readl(&mci->rdr);
134 status = 0;
135 }
136io_fail:
137 return status;
138}
139
140/* Entered into function pointer in mci_send_cmd */
141static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
142{
143 u32 status;
144
145 do {
146 status = readl(&mci->sr);
147 if (status & (error_flags | MMCI_BIT(UNRE)))
148 goto io_fail;
149 } while (!(status & MMCI_BIT(TXRDY)));
150
151 if (status & MMCI_BIT(TXRDY)) {
152 writel(*data, &mci->tdr);
153 status = 0;
154 }
155io_fail:
156 return status;
157}
158
159/*
160 * Entered into mmc structure during driver init
161 *
162 * Sends a command out on the bus and deals with the block data.
163 * Takes the mmc pointer, a command pointer, and an optional data pointer.
164 */
165static int
166mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
167{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200168 atmel_mci_t *mci = mmc->priv;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200169 u32 cmdr;
170 u32 error_flags = 0;
171 u32 status;
172
173 if (!initialized) {
174 puts ("MCI not initialized!\n");
175 return COMM_ERR;
176 }
177
178 /* Figure out the transfer arguments */
179 cmdr = mci_encode_cmd(cmd, data, &error_flags);
180
Wu, Joshd1e486b2012-09-13 22:22:04 +0000181 /* For multi blocks read/write, set the block register */
182 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
183 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
184 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
185 &mci->blkr);
186
Reinhard Meyerc718a562010-08-13 10:31:06 +0200187 /* Send the command */
188 writel(cmd->cmdarg, &mci->argr);
189 writel(cmdr, &mci->cmdr);
190
191#ifdef DEBUG
192 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
193#endif
194
195 /* Wait for the command to complete */
196 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
197
Bo Shen03a743f2013-04-26 00:27:07 +0000198 if ((status & error_flags) & MMCI_BIT(RTOE)) {
199 dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
200 return TIMEOUT;
201 } else if (status & error_flags) {
Reinhard Meyerc718a562010-08-13 10:31:06 +0200202 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
203 return COMM_ERR;
204 }
205
206 /* Copy the response to the response buffer */
207 if (cmd->resp_type & MMC_RSP_136) {
208 cmd->response[0] = readl(&mci->rspr);
209 cmd->response[1] = readl(&mci->rspr1);
210 cmd->response[2] = readl(&mci->rspr2);
211 cmd->response[3] = readl(&mci->rspr3);
212 } else
213 cmd->response[0] = readl(&mci->rspr);
214
215 /* transfer all of the blocks */
216 if (data) {
217 u32 word_count, block_count;
218 u32* ioptr;
219 u32 sys_blocksize, dummy, i;
220 u32 (*mci_data_op)
221 (atmel_mci_t *mci, u32* data, u32 error_flags);
222
223 if (data->flags & MMC_DATA_READ) {
224 mci_data_op = mci_data_read;
225 sys_blocksize = mmc->read_bl_len;
226 ioptr = (u32*)data->dest;
227 } else {
228 mci_data_op = mci_data_write;
229 sys_blocksize = mmc->write_bl_len;
230 ioptr = (u32*)data->src;
231 }
232
233 status = 0;
234 for (block_count = 0;
235 block_count < data->blocks && !status;
236 block_count++) {
237 word_count = 0;
238 do {
239 status = mci_data_op(mci, ioptr, error_flags);
240 word_count++;
241 ioptr++;
242 } while (!status && word_count < (data->blocksize/4));
243#ifdef DEBUG
244 if (data->flags & MMC_DATA_READ)
245 {
Wu, Josh6bcb5622014-05-07 17:06:08 +0800246 u32 cnt = word_count * 4;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200247 printf("Read Data:\n");
Wu, Josh6bcb5622014-05-07 17:06:08 +0800248 print_buffer(0, data->dest + cnt * block_count,
249 1, cnt, 0);
Reinhard Meyerc718a562010-08-13 10:31:06 +0200250 }
251#endif
252#ifdef DEBUG
253 if (!status && word_count < (sys_blocksize / 4))
254 printf("filling rest of block...\n");
255#endif
256 /* fill the rest of a full block */
257 while (!status && word_count < (sys_blocksize / 4)) {
258 status = mci_data_op(mci, &dummy,
259 error_flags);
260 word_count++;
261 }
262 if (status) {
263 dump_cmd(cmdr, cmd->cmdarg, status,
264 "Data Transfer Failed");
265 return COMM_ERR;
266 }
267 }
268
269 /* Wait for Transfer End */
270 i = 0;
271 do {
272 status = readl(&mci->sr);
273
274 if (status & error_flags) {
275 dump_cmd(cmdr, cmd->cmdarg, status,
276 "DTIP Wait Failed");
277 return COMM_ERR;
278 }
279 i++;
280 } while ((status & MMCI_BIT(DTIP)) && i < 10000);
281 if (status & MMCI_BIT(DTIP)) {
282 dump_cmd(cmdr, cmd->cmdarg, status,
283 "XFER DTIP never unset, ignoring");
284 }
285 }
286
287 return 0;
288}
289
290/* Entered into mmc structure during driver init */
291static void mci_set_ios(struct mmc *mmc)
292{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200293 atmel_mci_t *mci = mmc->priv;
Bo Shen644b4762013-04-26 00:27:06 +0000294 int bus_width = mmc->bus_width;
295 unsigned int version = atmel_mci_get_version(mci);
296 int busw;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200297
298 /* Set the clock speed */
299 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
300
301 /*
302 * set the bus width and select slot for this interface
303 * there is no capability for multiple slots on the same interface yet
Reinhard Meyerc718a562010-08-13 10:31:06 +0200304 */
Bo Shen644b4762013-04-26 00:27:06 +0000305 if ((version & 0xf00) >= 0x300) {
306 switch (bus_width) {
307 case 8:
308 busw = 3;
309 break;
310 case 4:
311 busw = 2;
312 break;
313 default:
314 busw = 0;
315 break;
316 }
317
318 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
319 } else {
320 busw = (bus_width == 4) ? 1 : 0;
321
322 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
323 }
Reinhard Meyerc718a562010-08-13 10:31:06 +0200324}
325
326/* Entered into mmc structure during driver init */
327static int mci_init(struct mmc *mmc)
328{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200329 atmel_mci_t *mci = mmc->priv;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200330
331 /* Initialize controller */
332 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
333 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
334 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
Reinhard Meyerf2675572010-11-16 09:24:41 +0100335 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
Reinhard Meyerc718a562010-08-13 10:31:06 +0200336
Wu, Joshec35c912012-09-13 22:22:06 +0000337 /* This delay can be optimized, but stick with max value */
338 writel(0x7f, &mci->dtor);
Reinhard Meyerc718a562010-08-13 10:31:06 +0200339 /* Disable Interrupts */
340 writel(~0UL, &mci->idr);
341
342 /* Set default clocks and blocklen */
343 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
344
345 return 0;
346}
347
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200348static const struct mmc_ops atmel_mci_ops = {
349 .send_cmd = mci_send_cmd,
350 .set_ios = mci_set_ios,
351 .init = mci_init,
352};
353
Reinhard Meyerc718a562010-08-13 10:31:06 +0200354/*
355 * This is the only exported function
356 *
357 * Call it with the MCI register base address
358 */
359int atmel_mci_init(void *regs)
360{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200361 struct mmc *mmc;
362 struct mmc_config *cfg;
Bo Shen644b4762013-04-26 00:27:06 +0000363 struct atmel_mci *mci;
364 unsigned int version;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200365
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200366 cfg = malloc(sizeof(*cfg));
367 if (cfg == NULL)
Reinhard Meyerc718a562010-08-13 10:31:06 +0200368 return -1;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200369 memset(cfg, 0, sizeof(*cfg));
Bo Shen644b4762013-04-26 00:27:06 +0000370
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200371 mci = (struct atmel_mci *)regs;
372
373 cfg->name = "mci";
374 cfg->ops = &atmel_mci_ops;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200375
376 /* need to be able to pass these in on a board by board basis */
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200377 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
Bo Shen644b4762013-04-26 00:27:06 +0000378 version = atmel_mci_get_version(mci);
379 if ((version & 0xf00) >= 0x300)
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200380 cfg->host_caps = MMC_MODE_8BIT;
Bo Shen644b4762013-04-26 00:27:06 +0000381
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200382 cfg->host_caps |= MMC_MODE_4BIT;
Bo Shen644b4762013-04-26 00:27:06 +0000383
Reinhard Meyerc718a562010-08-13 10:31:06 +0200384 /*
385 * min and max frequencies determined by
386 * max and min of clock divider
387 */
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200388 cfg->f_min = get_mci_clk_rate() / (2*256);
389 cfg->f_max = get_mci_clk_rate() / (2*1);
390
391 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Reinhard Meyerc718a562010-08-13 10:31:06 +0200392
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200393 mmc = mmc_create(cfg, regs);
John Rigbyf2f43662011-04-18 05:50:08 +0000394
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200395 if (mmc == NULL) {
396 free(cfg);
397 return -1;
398 }
399 /* NOTE: possibly leaking the cfg structure */
Reinhard Meyerc718a562010-08-13 10:31:06 +0200400
401 return 0;
402}