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Kumar Gala124b0822008-08-26 15:01:29 -05001/*
York Sun2896cb72014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala124b0822008-08-26 15:01:29 -05003 *
Tom Rinie2378802016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Kumar Gala124b0822008-08-26 15:01:29 -05005 */
6
7#include <common.h>
York Sun461c9392013-09-30 14:20:51 -07008#ifdef CONFIG_PPC
Kumar Gala124b0822008-08-26 15:01:29 -05009#include <asm/fsl_law.h>
York Sun461c9392013-09-30 14:20:51 -070010#endif
Kyle Moffette37716a2011-03-15 11:23:47 -040011#include <div64.h>
Kumar Gala124b0822008-08-26 15:01:29 -050012
York Sunf0626592013-09-30 09:22:09 -070013#include <fsl_ddr.h>
York Suna21803d2013-11-18 10:29:32 -080014#include <fsl_immap.h>
York Sunf0626592013-09-30 09:22:09 -070015#include <asm/io.h>
Simon Glass89e0a3a2017-05-17 08:23:10 -060016#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
17 defined(CONFIG_ARM)
Simon Glass243182c2017-05-17 08:23:06 -060018#include <asm/arch/clock.h>
19#endif
Kumar Gala124b0822008-08-26 15:01:29 -050020
Kyle Moffette37716a2011-03-15 11:23:47 -040021/* To avoid 64-bit full-divides, we factor this here */
Kyle Moffett313e8272011-04-14 13:39:30 -040022#define ULL_2E12 2000000000000ULL
23#define UL_5POW12 244140625UL
24#define UL_2POW13 (1UL << 13)
Kyle Moffette37716a2011-03-15 11:23:47 -040025
Kyle Moffett313e8272011-04-14 13:39:30 -040026#define ULL_8FS 0xFFFFFFFFULL
Kyle Moffette37716a2011-03-15 11:23:47 -040027
York Sun55eb5fa2015-03-19 09:30:26 -070028u32 fsl_ddr_get_version(unsigned int ctrl_num)
York Sun2896cb72014-03-27 17:54:47 -070029{
30 struct ccsr_ddr __iomem *ddr;
31 u32 ver_major_minor_errata;
32
York Sun55eb5fa2015-03-19 09:30:26 -070033 switch (ctrl_num) {
34 case 0:
35 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
36 break;
York Sunfe845072016-12-28 08:43:45 -080037#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
York Sun55eb5fa2015-03-19 09:30:26 -070038 case 1:
39 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
40 break;
41#endif
York Sunfe845072016-12-28 08:43:45 -080042#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
York Sun55eb5fa2015-03-19 09:30:26 -070043 case 2:
44 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
45 break;
46#endif
York Sunfe845072016-12-28 08:43:45 -080047#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
York Sun55eb5fa2015-03-19 09:30:26 -070048 case 3:
49 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
50 break;
51#endif
52 default:
53 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
54 return 0;
55 }
York Sun2896cb72014-03-27 17:54:47 -070056 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
57 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
58
59 return ver_major_minor_errata;
60}
61
Kumar Gala124b0822008-08-26 15:01:29 -050062/*
York Sundc4d40c2011-08-26 11:32:42 -070063 * Round up mclk_ps to nearest 1 ps in memory controller code
64 * if the error is 0.5ps or more.
Kumar Gala124b0822008-08-26 15:01:29 -050065 *
66 * If an imprecise data rate is too high due to rounding error
67 * propagation, compute a suitably rounded mclk_ps to compute
68 * a working memory controller configuration.
69 */
York Sun2c0b62d2015-01-06 13:18:50 -080070unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
Kumar Gala124b0822008-08-26 15:01:29 -050071{
York Sun2c0b62d2015-01-06 13:18:50 -080072 unsigned int data_rate = get_ddr_freq(ctrl_num);
Kyle Moffette37716a2011-03-15 11:23:47 -040073 unsigned int result;
74
75 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
York Sundc4d40c2011-08-26 11:32:42 -070076 unsigned long long rem, mclk_ps = ULL_2E12;
Kumar Gala124b0822008-08-26 15:01:29 -050077
Kyle Moffette37716a2011-03-15 11:23:47 -040078 /* Now perform the big divide, the result fits in 32-bits */
York Sundc4d40c2011-08-26 11:32:42 -070079 rem = do_div(mclk_ps, data_rate);
80 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
Kyle Moffette37716a2011-03-15 11:23:47 -040081
York Sundc4d40c2011-08-26 11:32:42 -070082 return result;
Kumar Gala124b0822008-08-26 15:01:29 -050083}
84
85/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
York Sun2c0b62d2015-01-06 13:18:50 -080086unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
Kumar Gala124b0822008-08-26 15:01:29 -050087{
Kyle Moffette37716a2011-03-15 11:23:47 -040088 unsigned long long clks, clks_rem;
York Sun2c0b62d2015-01-06 13:18:50 -080089 unsigned long data_rate = get_ddr_freq(ctrl_num);
Kumar Gala124b0822008-08-26 15:01:29 -050090
Kyle Moffette37716a2011-03-15 11:23:47 -040091 /* Short circuit for zero picos */
Kumar Gala124b0822008-08-26 15:01:29 -050092 if (!picos)
93 return 0;
94
Kyle Moffette37716a2011-03-15 11:23:47 -040095 /* First multiply the time by the data rate (32x32 => 64) */
York Sundc4d40c2011-08-26 11:32:42 -070096 clks = picos * (unsigned long long)data_rate;
Kyle Moffette37716a2011-03-15 11:23:47 -040097 /*
98 * Now divide by 5^12 and track the 32-bit remainder, then divide
99 * by 2*(2^12) using shifts (and updating the remainder).
100 */
Kyle Moffett313e8272011-04-14 13:39:30 -0400101 clks_rem = do_div(clks, UL_5POW12);
York Sundc4d40c2011-08-26 11:32:42 -0700102 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
Kyle Moffette37716a2011-03-15 11:23:47 -0400103 clks >>= 13;
104
York Sundc4d40c2011-08-26 11:32:42 -0700105 /* If we had a remainder greater than the 1ps error, then round up */
106 if (clks_rem > data_rate)
Kumar Gala124b0822008-08-26 15:01:29 -0500107 clks++;
Kumar Gala124b0822008-08-26 15:01:29 -0500108
Kyle Moffette37716a2011-03-15 11:23:47 -0400109 /* Clamp to the maximum representable value */
Kyle Moffett313e8272011-04-14 13:39:30 -0400110 if (clks > ULL_8FS)
111 clks = ULL_8FS;
Kumar Gala124b0822008-08-26 15:01:29 -0500112 return (unsigned int) clks;
113}
114
York Sun2c0b62d2015-01-06 13:18:50 -0800115unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
Kumar Gala124b0822008-08-26 15:01:29 -0500116{
York Sun2c0b62d2015-01-06 13:18:50 -0800117 return get_memory_clk_period_ps(ctrl_num) * mclk;
Kumar Gala124b0822008-08-26 15:01:29 -0500118}
119
York Sun461c9392013-09-30 14:20:51 -0700120#ifdef CONFIG_PPC
Kumar Gala124b0822008-08-26 15:01:29 -0500121void
122__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
York Sune8dc17b2012-08-17 08:22:39 +0000123 unsigned int law_memctl,
Kumar Gala124b0822008-08-26 15:01:29 -0500124 unsigned int ctrl_num)
125{
Kumar Gala68ef4bd2009-06-11 23:42:35 -0500126 unsigned long long base = memctl_common_params->base_address;
127 unsigned long long size = memctl_common_params->total_mem;
128
Kumar Gala124b0822008-08-26 15:01:29 -0500129 /*
130 * If no DIMMs on this controller, do not proceed any further.
131 */
132 if (!memctl_common_params->ndimms_present) {
133 return;
134 }
135
Kumar Gala68ef4bd2009-06-11 23:42:35 -0500136#if !defined(CONFIG_PHYS_64BIT)
137 if (base >= CONFIG_MAX_MEM_MAPPED)
138 return;
139 if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
140 size = CONFIG_MAX_MEM_MAPPED - base;
141#endif
York Sune8dc17b2012-08-17 08:22:39 +0000142 if (set_ddr_laws(base, size, law_memctl) < 0) {
143 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
144 law_memctl);
145 return ;
Kumar Gala124b0822008-08-26 15:01:29 -0500146 }
York Sune8dc17b2012-08-17 08:22:39 +0000147 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
148 base, size, law_memctl);
Kumar Gala124b0822008-08-26 15:01:29 -0500149}
150
151__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
152fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
153 unsigned int memctl_interleaved,
154 unsigned int ctrl_num);
York Sun461c9392013-09-30 14:20:51 -0700155#endif
Peter Tyserf4018f92009-07-17 10:14:48 -0500156
York Sune8dc17b2012-08-17 08:22:39 +0000157void fsl_ddr_set_intl3r(const unsigned int granule_size)
158{
159#ifdef CONFIG_E6500
160 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
161 *mcintl3r = 0x80000000 | (granule_size & 0x1f);
162 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
163#endif
164}
165
York Suna28496f2012-10-08 07:44:25 +0000166u32 fsl_ddr_get_intl3r(void)
167{
168 u32 val = 0;
169#ifdef CONFIG_E6500
170 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
171 val = *mcintl3r;
172#endif
173 return val;
174}
175
York Sun79a779b2014-08-01 15:51:00 -0700176void print_ddr_info(unsigned int start_ctrl)
Peter Tyserf4018f92009-07-17 10:14:48 -0500177{
York Suna21803d2013-11-18 10:29:32 -0800178 struct ccsr_ddr __iomem *ddr =
179 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
Andy Fleming992562c2012-10-23 19:03:46 -0500180
York Sunfe845072016-12-28 08:43:45 -0800181#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
York Sune8dc17b2012-08-17 08:22:39 +0000182 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
183#endif
York Sunfe845072016-12-28 08:43:45 -0800184#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
York Sun29647ab2014-02-10 13:59:42 -0800185 uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
Peter Tyserf4018f92009-07-17 10:14:48 -0500186#endif
York Sun29647ab2014-02-10 13:59:42 -0800187 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
Peter Tyserf4018f92009-07-17 10:14:48 -0500188 int cas_lat;
189
York Sunfe845072016-12-28 08:43:45 -0800190#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
York Sun79a779b2014-08-01 15:51:00 -0700191 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
192 (start_ctrl == 1)) {
York Sunf0626592013-09-30 09:22:09 -0700193 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
York Sun29647ab2014-02-10 13:59:42 -0800194 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
York Sun98df4d12012-10-08 07:44:23 +0000195 }
196#endif
York Sunfe845072016-12-28 08:43:45 -0800197#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
York Sun79a779b2014-08-01 15:51:00 -0700198 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
199 (start_ctrl == 2)) {
York Sunf0626592013-09-30 09:22:09 -0700200 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
York Sun29647ab2014-02-10 13:59:42 -0800201 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
York Sun98df4d12012-10-08 07:44:23 +0000202 }
203#endif
York Sun79a779b2014-08-01 15:51:00 -0700204
205 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
206 puts(" (DDR not enabled)\n");
207 return;
208 }
209
Peter Tyserf4018f92009-07-17 10:14:48 -0500210 puts(" (DDR");
211 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
212 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
213 case SDRAM_TYPE_DDR1:
214 puts("1");
215 break;
216 case SDRAM_TYPE_DDR2:
217 puts("2");
218 break;
219 case SDRAM_TYPE_DDR3:
220 puts("3");
221 break;
York Sun2896cb72014-03-27 17:54:47 -0700222 case SDRAM_TYPE_DDR4:
223 puts("4");
224 break;
Peter Tyserf4018f92009-07-17 10:14:48 -0500225 default:
226 puts("?");
227 break;
228 }
229
230 if (sdram_cfg & SDRAM_CFG_32_BE)
231 puts(", 32-bit");
Poonam Aggrwal42d36402011-02-07 15:09:51 +0530232 else if (sdram_cfg & SDRAM_CFG_16_BE)
233 puts(", 16-bit");
Peter Tyserf4018f92009-07-17 10:14:48 -0500234 else
235 puts(", 64-bit");
236
237 /* Calculate CAS latency based on timing cfg values */
York Sun2896cb72014-03-27 17:54:47 -0700238 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
York Sun55eb5fa2015-03-19 09:30:26 -0700239 if (fsl_ddr_get_version(0) <= 0x40400)
York Sun2896cb72014-03-27 17:54:47 -0700240 cas_lat += 1;
241 else
242 cas_lat += 2;
243 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
Peter Tyserf4018f92009-07-17 10:14:48 -0500244 printf(", CL=%d", cas_lat >> 1);
245 if (cas_lat & 0x1)
246 puts(".5");
247
248 if (sdram_cfg & SDRAM_CFG_ECC_EN)
249 puts(", ECC on)");
250 else
251 puts(", ECC off)");
252
York Sunfe845072016-12-28 08:43:45 -0800253#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
York Sune8dc17b2012-08-17 08:22:39 +0000254#ifdef CONFIG_E6500
255 if (*mcintl3r & 0x80000000) {
256 puts("\n");
257 puts(" DDR Controller Interleaving Mode: ");
258 switch (*mcintl3r & 0x1f) {
259 case FSL_DDR_3WAY_1KB_INTERLEAVING:
260 puts("3-way 1KB");
261 break;
262 case FSL_DDR_3WAY_4KB_INTERLEAVING:
263 puts("3-way 4KB");
264 break;
265 case FSL_DDR_3WAY_8KB_INTERLEAVING:
266 puts("3-way 8KB");
267 break;
268 default:
269 puts("3-way UNKNOWN");
270 break;
271 }
272 }
273#endif
274#endif
York Sunfe845072016-12-28 08:43:45 -0800275#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
York Sun79a779b2014-08-01 15:51:00 -0700276 if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
Peter Tyserf4018f92009-07-17 10:14:48 -0500277 puts("\n");
278 puts(" DDR Controller Interleaving Mode: ");
279
280 switch ((cs0_config >> 24) & 0xf) {
York Sunc459ae62014-02-10 13:59:44 -0800281 case FSL_DDR_256B_INTERLEAVING:
282 puts("256B");
283 break;
Peter Tyserf4018f92009-07-17 10:14:48 -0500284 case FSL_DDR_CACHE_LINE_INTERLEAVING:
285 puts("cache line");
286 break;
287 case FSL_DDR_PAGE_INTERLEAVING:
288 puts("page");
289 break;
290 case FSL_DDR_BANK_INTERLEAVING:
291 puts("bank");
292 break;
293 case FSL_DDR_SUPERBANK_INTERLEAVING:
294 puts("super-bank");
295 break;
296 default:
297 puts("invalid");
298 break;
299 }
300 }
301#endif
302
303 if ((sdram_cfg >> 8) & 0x7f) {
304 puts("\n");
305 puts(" DDR Chip-Select Interleaving Mode: ");
306 switch(sdram_cfg >> 8 & 0x7f) {
307 case FSL_DDR_CS0_CS1_CS2_CS3:
308 puts("CS0+CS1+CS2+CS3");
309 break;
310 case FSL_DDR_CS0_CS1:
311 puts("CS0+CS1");
312 break;
313 case FSL_DDR_CS2_CS3:
314 puts("CS2+CS3");
315 break;
316 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
317 puts("CS0+CS1 and CS2+CS3");
318 break;
319 default:
320 puts("invalid");
321 break;
322 }
323 }
324}
York Sun79a779b2014-08-01 15:51:00 -0700325
326void __weak detail_board_ddr_info(void)
327{
328 print_ddr_info(0);
329}
330
331void board_add_ram_info(int use_default)
332{
333 detail_board_ddr_info();
334}
York Sun8ced0502015-01-06 13:18:55 -0800335
336#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
337#define DDRC_DEBUG20_INIT_DONE 0x80000000
338#define DDRC_DEBUG2_RF 0x00000040
339void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
340 unsigned int last_ctrl)
341{
342 unsigned int i;
343 u32 ddrc_debug20;
York Sunfe845072016-12-28 08:43:45 -0800344 u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
345 u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
York Sun8ced0502015-01-06 13:18:55 -0800346 struct ccsr_ddr __iomem *ddr;
347
348 for (i = first_ctrl; i <= last_ctrl; i++) {
349 switch (i) {
350 case 0:
351 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
352 break;
York Sunfe845072016-12-28 08:43:45 -0800353#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
York Sun8ced0502015-01-06 13:18:55 -0800354 case 1:
355 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
356 break;
357#endif
York Sunfe845072016-12-28 08:43:45 -0800358#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
York Sun8ced0502015-01-06 13:18:55 -0800359 case 2:
360 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
361 break;
362#endif
York Sunfe845072016-12-28 08:43:45 -0800363#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
York Sun8ced0502015-01-06 13:18:55 -0800364 case 3:
365 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
366 break;
367#endif
368 default:
369 printf("%s unexpected ctrl = %u\n", __func__, i);
370 return;
371 }
372 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
373 ddrc_debug2_p[i] = &ddr->debug[1];
374 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
375 /* keep polling until DDRC init is done */
376 udelay(100);
377 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
378 }
379 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
380 }
381 /*
382 * Sync refresh
383 * This is put together to make sure the refresh reqeusts are sent
384 * closely to each other.
385 */
386 for (i = first_ctrl; i <= last_ctrl; i++)
387 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
388}
389#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
York Sund957a672015-11-04 09:53:10 -0800390
391void remove_unused_controllers(fsl_ddr_info_t *info)
392{
393#ifdef CONFIG_FSL_LSCH3
394 int i;
395 u64 nodeid;
396 void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
397 bool ddr0_used = false;
398 bool ddr1_used = false;
399
400 for (i = 0; i < 8; i++) {
401 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
402 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
403 ddr0_used = true;
404 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
405 ddr1_used = true;
406 } else {
407 printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
408 nodeid);
409 }
410 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
411 }
412 if (!ddr0_used && !ddr1_used) {
413 printf("Invalid configuration in HN-F SAM control\n");
414 return;
415 }
416
417 if (!ddr0_used && info->first_ctrl == 0) {
418 info->first_ctrl = 1;
419 info->num_ctrls = 1;
420 debug("First DDR controller disabled\n");
421 return;
422 }
423
424 if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
425 info->num_ctrls = 1;
426 debug("Second DDR controller disabled\n");
427 }
428#endif
429}