blob: d43da454114ded3f3debfb78c5eea0fee0b5780a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warrenfccc9c52016-08-08 11:28:25 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warrenfccc9c52016-08-08 11:28:25 -06004 */
5
6#include <common.h>
7#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -07009#include <malloc.h>
Stephen Warrenfccc9c52016-08-08 11:28:25 -060010#include <misc.h>
11#include <reset-uclass.h>
12#include <asm/arch-tegra/bpmp_abi.h>
13
Stephen Warrenfccc9c52016-08-08 11:28:25 -060014static int tegra186_reset_common(struct reset_ctl *reset_ctl,
15 enum mrq_reset_commands cmd)
16{
17 struct mrq_reset_request req;
18 int ret;
19
20 req.cmd = cmd;
21 req.reset_id = reset_ctl->id;
22
23 ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
24 NULL, 0);
25 if (ret < 0)
26 return ret;
27
28 return 0;
29}
30
31static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
32{
33 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
34 reset_ctl->dev, reset_ctl->id);
35
36 return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
37}
38
39static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
40{
41 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
42 reset_ctl->dev, reset_ctl->id);
43
44 return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
45}
46
47struct reset_ops tegra186_reset_ops = {
Stephen Warrenfccc9c52016-08-08 11:28:25 -060048 .rst_assert = tegra186_reset_assert,
49 .rst_deassert = tegra186_reset_deassert,
50};
51
Stephen Warrenfccc9c52016-08-08 11:28:25 -060052U_BOOT_DRIVER(tegra186_reset) = {
53 .name = "tegra186_reset",
54 .id = UCLASS_RESET,
Stephen Warrenfccc9c52016-08-08 11:28:25 -060055 .ops = &tegra186_reset_ops,
56};