Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Porting to u-boot: |
| 3 | * |
| 4 | * (C) Copyright 2010 |
| 5 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de |
| 6 | * |
| 7 | * Linux IPU driver for MX51: |
| 8 | * |
| 9 | * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. |
| 10 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 11 | * SPDX-License-Identifier: GPL-2.0+ |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | /* #define DEBUG */ |
| 15 | |
| 16 | #include <common.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <asm/errno.h> |
| 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/imx-regs.h> |
| 21 | #include <asm/arch/sys_proto.h> |
| 22 | #include "ipu.h" |
| 23 | #include "ipu_regs.h" |
| 24 | |
| 25 | enum csc_type_t { |
| 26 | RGB2YUV = 0, |
| 27 | YUV2RGB, |
| 28 | RGB2RGB, |
| 29 | YUV2YUV, |
| 30 | CSC_NONE, |
| 31 | CSC_NUM |
| 32 | }; |
| 33 | |
| 34 | struct dp_csc_param_t { |
| 35 | int mode; |
| 36 | void *coeff; |
| 37 | }; |
| 38 | |
| 39 | #define SYNC_WAVE 0 |
| 40 | |
| 41 | /* DC display ID assignments */ |
| 42 | #define DC_DISP_ID_SYNC(di) (di) |
| 43 | #define DC_DISP_ID_SERIAL 2 |
| 44 | #define DC_DISP_ID_ASYNC 3 |
| 45 | |
| 46 | int dmfc_type_setup; |
| 47 | static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; |
| 48 | int g_di1_tvout; |
| 49 | |
| 50 | extern struct clk *g_ipu_clk; |
Eric Nelson | 5018c55 | 2012-05-31 07:24:02 +0000 | [diff] [blame] | 51 | extern struct clk *g_ldb_clk; |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 52 | extern struct clk *g_di_clk[2]; |
| 53 | extern struct clk *g_pixel_clk[2]; |
| 54 | |
| 55 | extern unsigned char g_ipu_clk_enabled; |
| 56 | extern unsigned char g_dc_di_assignment[]; |
| 57 | |
| 58 | void ipu_dmfc_init(int dmfc_type, int first) |
| 59 | { |
| 60 | u32 dmfc_wr_chan, dmfc_dp_chan; |
| 61 | |
| 62 | if (first) { |
| 63 | if (dmfc_type_setup > dmfc_type) |
| 64 | dmfc_type = dmfc_type_setup; |
| 65 | else |
| 66 | dmfc_type_setup = dmfc_type; |
| 67 | |
| 68 | /* disable DMFC-IC channel*/ |
| 69 | __raw_writel(0x2, DMFC_IC_CTRL); |
| 70 | } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) { |
| 71 | printf("DMFC high resolution has set, will not change\n"); |
| 72 | return; |
| 73 | } else |
| 74 | dmfc_type_setup = dmfc_type; |
| 75 | |
| 76 | if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) { |
| 77 | /* 1 - segment 0~3; |
| 78 | * 5B - segement 4, 5; |
| 79 | * 5F - segement 6, 7; |
| 80 | * 1C, 2C and 6B, 6F unused; |
| 81 | */ |
| 82 | debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n"); |
| 83 | dmfc_wr_chan = 0x00000088; |
| 84 | dmfc_dp_chan = 0x00009694; |
| 85 | dmfc_size_28 = 256 * 4; |
| 86 | dmfc_size_29 = 0; |
| 87 | dmfc_size_24 = 0; |
| 88 | dmfc_size_27 = 128 * 4; |
| 89 | dmfc_size_23 = 128 * 4; |
| 90 | } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) { |
| 91 | /* 1 - segment 0, 1; |
| 92 | * 5B - segement 2~5; |
| 93 | * 5F - segement 6,7; |
| 94 | * 1C, 2C and 6B, 6F unused; |
| 95 | */ |
| 96 | debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n"); |
| 97 | dmfc_wr_chan = 0x00000090; |
| 98 | dmfc_dp_chan = 0x0000968a; |
| 99 | dmfc_size_28 = 128 * 4; |
| 100 | dmfc_size_29 = 0; |
| 101 | dmfc_size_24 = 0; |
| 102 | dmfc_size_27 = 128 * 4; |
| 103 | dmfc_size_23 = 256 * 4; |
| 104 | } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) { |
| 105 | /* 5B - segement 0~3; |
| 106 | * 5F - segement 4~7; |
| 107 | * 1, 1C, 2C and 6B, 6F unused; |
| 108 | */ |
| 109 | debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n"); |
| 110 | dmfc_wr_chan = 0x00000000; |
| 111 | dmfc_dp_chan = 0x00008c88; |
| 112 | dmfc_size_28 = 0; |
| 113 | dmfc_size_29 = 0; |
| 114 | dmfc_size_24 = 0; |
| 115 | dmfc_size_27 = 256 * 4; |
| 116 | dmfc_size_23 = 256 * 4; |
| 117 | } else { |
| 118 | /* 1 - segment 0, 1; |
| 119 | * 5B - segement 4, 5; |
| 120 | * 5F - segement 6, 7; |
| 121 | * 1C, 2C and 6B, 6F unused; |
| 122 | */ |
| 123 | debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n"); |
| 124 | dmfc_wr_chan = 0x00000090; |
| 125 | dmfc_dp_chan = 0x00009694; |
| 126 | dmfc_size_28 = 128 * 4; |
| 127 | dmfc_size_29 = 0; |
| 128 | dmfc_size_24 = 0; |
| 129 | dmfc_size_27 = 128 * 4; |
| 130 | dmfc_size_23 = 128 * 4; |
| 131 | } |
| 132 | __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); |
| 133 | __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); |
| 134 | __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); |
| 135 | /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */ |
| 136 | __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); |
| 137 | } |
| 138 | |
| 139 | void ipu_dmfc_set_wait4eot(int dma_chan, int width) |
| 140 | { |
| 141 | u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); |
| 142 | |
| 143 | if (width >= HIGH_RESOLUTION_WIDTH) { |
| 144 | if (dma_chan == 23) |
| 145 | ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0); |
| 146 | else if (dma_chan == 28) |
| 147 | ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0); |
| 148 | } |
| 149 | |
| 150 | if (dma_chan == 23) { /*5B*/ |
| 151 | if (dmfc_size_23 / width > 3) |
| 152 | dmfc_gen1 |= 1UL << 20; |
| 153 | else |
| 154 | dmfc_gen1 &= ~(1UL << 20); |
| 155 | } else if (dma_chan == 24) { /*6B*/ |
| 156 | if (dmfc_size_24 / width > 1) |
| 157 | dmfc_gen1 |= 1UL << 22; |
| 158 | else |
| 159 | dmfc_gen1 &= ~(1UL << 22); |
| 160 | } else if (dma_chan == 27) { /*5F*/ |
| 161 | if (dmfc_size_27 / width > 2) |
| 162 | dmfc_gen1 |= 1UL << 21; |
| 163 | else |
| 164 | dmfc_gen1 &= ~(1UL << 21); |
| 165 | } else if (dma_chan == 28) { /*1*/ |
| 166 | if (dmfc_size_28 / width > 2) |
| 167 | dmfc_gen1 |= 1UL << 16; |
| 168 | else |
| 169 | dmfc_gen1 &= ~(1UL << 16); |
| 170 | } else if (dma_chan == 29) { /*6F*/ |
| 171 | if (dmfc_size_29 / width > 1) |
| 172 | dmfc_gen1 |= 1UL << 23; |
| 173 | else |
| 174 | dmfc_gen1 &= ~(1UL << 23); |
| 175 | } |
| 176 | |
| 177 | __raw_writel(dmfc_gen1, DMFC_GENERAL1); |
| 178 | } |
| 179 | |
| 180 | static void ipu_di_data_wave_config(int di, |
| 181 | int wave_gen, |
| 182 | int access_size, int component_size) |
| 183 | { |
| 184 | u32 reg; |
| 185 | reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | |
| 186 | (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); |
| 187 | __raw_writel(reg, DI_DW_GEN(di, wave_gen)); |
| 188 | } |
| 189 | |
| 190 | static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set, |
| 191 | int up, int down) |
| 192 | { |
| 193 | u32 reg; |
| 194 | |
| 195 | reg = __raw_readl(DI_DW_GEN(di, wave_gen)); |
| 196 | reg &= ~(0x3 << (di_pin * 2)); |
| 197 | reg |= set << (di_pin * 2); |
| 198 | __raw_writel(reg, DI_DW_GEN(di, wave_gen)); |
| 199 | |
| 200 | __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); |
| 201 | } |
| 202 | |
| 203 | static void ipu_di_sync_config(int di, int wave_gen, |
| 204 | int run_count, int run_src, |
| 205 | int offset_count, int offset_src, |
| 206 | int repeat_count, int cnt_clr_src, |
| 207 | int cnt_polarity_gen_en, |
| 208 | int cnt_polarity_clr_src, |
| 209 | int cnt_polarity_trigger_src, |
| 210 | int cnt_up, int cnt_down) |
| 211 | { |
| 212 | u32 reg; |
| 213 | |
| 214 | if ((run_count >= 0x1000) || (offset_count >= 0x1000) || |
| 215 | (repeat_count >= 0x1000) || |
| 216 | (cnt_up >= 0x400) || (cnt_down >= 0x400)) { |
| 217 | printf("DI%d counters out of range.\n", di); |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | reg = (run_count << 19) | (++run_src << 16) | |
| 222 | (offset_count << 3) | ++offset_src; |
| 223 | __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); |
| 224 | reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | |
| 225 | (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9); |
| 226 | reg |= (cnt_down << 16) | cnt_up; |
| 227 | if (repeat_count == 0) { |
| 228 | /* Enable auto reload */ |
| 229 | reg |= 0x10000000; |
| 230 | } |
| 231 | __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); |
| 232 | reg = __raw_readl(DI_STP_REP(di, wave_gen)); |
| 233 | reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); |
| 234 | reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); |
| 235 | __raw_writel(reg, DI_STP_REP(di, wave_gen)); |
| 236 | } |
| 237 | |
| 238 | static void ipu_dc_map_config(int map, int byte_num, int offset, int mask) |
| 239 | { |
| 240 | int ptr = map * 3 + byte_num; |
| 241 | u32 reg; |
| 242 | |
| 243 | reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); |
| 244 | reg &= ~(0xFFFF << (16 * (ptr & 0x1))); |
| 245 | reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); |
| 246 | __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); |
| 247 | |
| 248 | reg = __raw_readl(DC_MAP_CONF_PTR(map)); |
| 249 | reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); |
| 250 | reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); |
| 251 | __raw_writel(reg, DC_MAP_CONF_PTR(map)); |
| 252 | } |
| 253 | |
| 254 | static void ipu_dc_map_clear(int map) |
| 255 | { |
| 256 | u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); |
| 257 | __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), |
| 258 | DC_MAP_CONF_PTR(map)); |
| 259 | } |
| 260 | |
| 261 | static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map, |
| 262 | int wave, int glue, int sync) |
| 263 | { |
| 264 | u32 reg; |
| 265 | int stop = 1; |
| 266 | |
| 267 | reg = sync; |
| 268 | reg |= (glue << 4); |
| 269 | reg |= (++wave << 11); |
| 270 | reg |= (++map << 15); |
| 271 | reg |= (operand << 20) & 0xFFF00000; |
| 272 | __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); |
| 273 | |
| 274 | reg = (operand >> 12); |
| 275 | reg |= opcode << 4; |
| 276 | reg |= (stop << 9); |
| 277 | __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); |
| 278 | } |
| 279 | |
| 280 | static void ipu_dc_link_event(int chan, int event, int addr, int priority) |
| 281 | { |
| 282 | u32 reg; |
| 283 | |
| 284 | reg = __raw_readl(DC_RL_CH(chan, event)); |
| 285 | reg &= ~(0xFFFF << (16 * (event & 0x1))); |
| 286 | reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); |
| 287 | __raw_writel(reg, DC_RL_CH(chan, event)); |
| 288 | } |
| 289 | |
| 290 | /* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250; |
| 291 | * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.; |
| 292 | * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.; |
| 293 | */ |
| 294 | static const int rgb2ycbcr_coeff[5][3] = { |
| 295 | {0x4D, 0x96, 0x1D}, |
| 296 | {0x3D5, 0x3AB, 0x80}, |
| 297 | {0x80, 0x395, 0x3EB}, |
| 298 | {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ |
| 299 | {0x2, 0x2, 0x2}, /* S0, S1, S2 */ |
| 300 | }; |
| 301 | |
| 302 | /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); |
| 303 | * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); |
| 304 | * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); |
| 305 | */ |
| 306 | static const int ycbcr2rgb_coeff[5][3] = { |
| 307 | {0x095, 0x000, 0x0CC}, |
| 308 | {0x095, 0x3CE, 0x398}, |
| 309 | {0x095, 0x0FF, 0x000}, |
| 310 | {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ |
| 311 | {0x1, 0x1, 0x1}, /*S0,S1,S2 */ |
| 312 | }; |
| 313 | |
| 314 | #define mask_a(a) ((u32)(a) & 0x3FF) |
| 315 | #define mask_b(b) ((u32)(b) & 0x3FFF) |
| 316 | |
| 317 | /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */ |
| 318 | static int rgb_to_yuv(int n, int red, int green, int blue) |
| 319 | { |
| 320 | int c; |
| 321 | c = red * rgb2ycbcr_coeff[n][0]; |
| 322 | c += green * rgb2ycbcr_coeff[n][1]; |
| 323 | c += blue * rgb2ycbcr_coeff[n][2]; |
| 324 | c /= 16; |
| 325 | c += rgb2ycbcr_coeff[3][n] * 4; |
| 326 | c += 8; |
| 327 | c /= 16; |
| 328 | if (c < 0) |
| 329 | c = 0; |
| 330 | if (c > 255) |
| 331 | c = 255; |
| 332 | return c; |
| 333 | } |
| 334 | |
| 335 | /* |
| 336 | * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE |
| 337 | * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE |
| 338 | */ |
| 339 | static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { |
| 340 | { |
| 341 | {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, |
| 342 | {0, 0}, |
| 343 | {0, 0}, |
| 344 | {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, |
| 345 | {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} |
| 346 | }, |
| 347 | { |
| 348 | {0, 0}, |
| 349 | {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, |
| 350 | {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, |
| 351 | {0, 0}, |
| 352 | {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} |
| 353 | }, |
| 354 | { |
| 355 | {0, 0}, |
| 356 | {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, |
| 357 | {0, 0}, |
| 358 | {0, 0}, |
| 359 | {0, 0} |
| 360 | }, |
| 361 | { |
| 362 | {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, |
| 363 | {0, 0}, |
| 364 | {0, 0}, |
| 365 | {0, 0}, |
| 366 | {0, 0} |
| 367 | }, |
| 368 | { |
| 369 | {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, |
| 370 | {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, |
| 371 | {0, 0}, |
| 372 | {0, 0}, |
| 373 | {0, 0} |
| 374 | } |
| 375 | }; |
| 376 | |
| 377 | static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; |
| 378 | static int color_key_4rgb = 1; |
| 379 | |
| 380 | void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, |
| 381 | unsigned char srm_mode_update) |
| 382 | { |
| 383 | u32 reg; |
| 384 | const int (*coeff)[5][3]; |
| 385 | |
| 386 | if (dp_csc_param.mode >= 0) { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 387 | reg = __raw_readl(DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 388 | reg &= ~DP_COM_CONF_CSC_DEF_MASK; |
| 389 | reg |= dp_csc_param.mode; |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 390 | __raw_writel(reg, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 391 | } |
| 392 | |
| 393 | coeff = dp_csc_param.coeff; |
| 394 | |
| 395 | if (coeff) { |
| 396 | __raw_writel(mask_a((*coeff)[0][0]) | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 397 | (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 398 | __raw_writel(mask_a((*coeff)[0][2]) | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 399 | (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 400 | __raw_writel(mask_a((*coeff)[1][1]) | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 401 | (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 402 | __raw_writel(mask_a((*coeff)[2][0]) | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 403 | (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 404 | __raw_writel(mask_a((*coeff)[2][2]) | |
| 405 | (mask_b((*coeff)[3][0]) << 16) | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 406 | ((*coeff)[4][0] << 30), DP_CSC_0()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 407 | __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) | |
| 408 | (mask_b((*coeff)[3][2]) << 16) | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 409 | ((*coeff)[4][2] << 30), DP_CSC_1()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 410 | } |
| 411 | |
| 412 | if (srm_mode_update) { |
| 413 | reg = __raw_readl(IPU_SRM_PRI2) | 0x8; |
| 414 | __raw_writel(reg, IPU_SRM_PRI2); |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, |
| 419 | uint32_t out_pixel_fmt) |
| 420 | { |
| 421 | int in_fmt, out_fmt; |
| 422 | int dp; |
| 423 | int partial = 0; |
| 424 | uint32_t reg; |
| 425 | |
| 426 | if (channel == MEM_FG_SYNC) { |
| 427 | dp = DP_SYNC; |
| 428 | partial = 1; |
| 429 | } else if (channel == MEM_BG_SYNC) { |
| 430 | dp = DP_SYNC; |
| 431 | partial = 0; |
| 432 | } else if (channel == MEM_BG_ASYNC0) { |
| 433 | dp = DP_ASYNC0; |
| 434 | partial = 0; |
| 435 | } else { |
| 436 | return -EINVAL; |
| 437 | } |
| 438 | |
| 439 | in_fmt = format_to_colorspace(in_pixel_fmt); |
| 440 | out_fmt = format_to_colorspace(out_pixel_fmt); |
| 441 | |
| 442 | if (partial) { |
| 443 | if (in_fmt == RGB) { |
| 444 | if (out_fmt == RGB) |
| 445 | fg_csc_type = RGB2RGB; |
| 446 | else |
| 447 | fg_csc_type = RGB2YUV; |
| 448 | } else { |
| 449 | if (out_fmt == RGB) |
| 450 | fg_csc_type = YUV2RGB; |
| 451 | else |
| 452 | fg_csc_type = YUV2YUV; |
| 453 | } |
| 454 | } else { |
| 455 | if (in_fmt == RGB) { |
| 456 | if (out_fmt == RGB) |
| 457 | bg_csc_type = RGB2RGB; |
| 458 | else |
| 459 | bg_csc_type = RGB2YUV; |
| 460 | } else { |
| 461 | if (out_fmt == RGB) |
| 462 | bg_csc_type = YUV2RGB; |
| 463 | else |
| 464 | bg_csc_type = YUV2YUV; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | /* Transform color key from rgb to yuv if CSC is enabled */ |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 469 | reg = __raw_readl(DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 470 | if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) && |
| 471 | (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || |
| 472 | ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || |
| 473 | ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || |
| 474 | ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) { |
| 475 | int red, green, blue; |
| 476 | int y, u, v; |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 477 | uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) & |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 478 | 0xFFFFFFL; |
| 479 | |
| 480 | debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n", |
| 481 | color_key); |
| 482 | |
| 483 | red = (color_key >> 16) & 0xFF; |
| 484 | green = (color_key >> 8) & 0xFF; |
| 485 | blue = color_key & 0xFF; |
| 486 | |
| 487 | y = rgb_to_yuv(0, red, green, blue); |
| 488 | u = rgb_to_yuv(1, red, green, blue); |
| 489 | v = rgb_to_yuv(2, red, green, blue); |
| 490 | color_key = (y << 16) | (u << 8) | v; |
| 491 | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 492 | reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; |
| 493 | __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 494 | color_key_4rgb = 0; |
| 495 | |
| 496 | debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n", |
| 497 | color_key); |
| 498 | } |
| 499 | |
| 500 | ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1); |
| 501 | |
| 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | void ipu_dp_uninit(ipu_channel_t channel) |
| 506 | { |
| 507 | int dp; |
| 508 | int partial = 0; |
| 509 | |
| 510 | if (channel == MEM_FG_SYNC) { |
| 511 | dp = DP_SYNC; |
| 512 | partial = 1; |
| 513 | } else if (channel == MEM_BG_SYNC) { |
| 514 | dp = DP_SYNC; |
| 515 | partial = 0; |
| 516 | } else if (channel == MEM_BG_ASYNC0) { |
| 517 | dp = DP_ASYNC0; |
| 518 | partial = 0; |
| 519 | } else { |
| 520 | return; |
| 521 | } |
| 522 | |
| 523 | if (partial) |
| 524 | fg_csc_type = CSC_NONE; |
| 525 | else |
| 526 | bg_csc_type = CSC_NONE; |
| 527 | |
| 528 | ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0); |
| 529 | } |
| 530 | |
| 531 | void ipu_dc_init(int dc_chan, int di, unsigned char interlaced) |
| 532 | { |
| 533 | u32 reg = 0; |
| 534 | |
| 535 | if ((dc_chan == 1) || (dc_chan == 5)) { |
| 536 | if (interlaced) { |
| 537 | ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3); |
| 538 | ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2); |
| 539 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1); |
| 540 | } else { |
| 541 | if (di) { |
| 542 | ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); |
| 543 | ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); |
| 544 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, |
| 545 | 4, 1); |
| 546 | } else { |
| 547 | ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3); |
| 548 | ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2); |
| 549 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, |
| 550 | 7, 1); |
| 551 | } |
| 552 | } |
| 553 | ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); |
| 554 | ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); |
| 555 | ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); |
| 556 | ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); |
| 557 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); |
| 558 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); |
| 559 | |
| 560 | reg = 0x2; |
| 561 | reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; |
| 562 | reg |= di << 2; |
| 563 | if (interlaced) |
| 564 | reg |= DC_WR_CH_CONF_FIELD_MODE; |
| 565 | } else if ((dc_chan == 8) || (dc_chan == 9)) { |
| 566 | /* async channels */ |
| 567 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1); |
| 568 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1); |
| 569 | |
| 570 | reg = 0x3; |
| 571 | reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; |
| 572 | } |
| 573 | __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); |
| 574 | |
| 575 | __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan)); |
| 576 | |
| 577 | __raw_writel(0x00000084, DC_GEN); |
| 578 | } |
| 579 | |
| 580 | void ipu_dc_uninit(int dc_chan) |
| 581 | { |
| 582 | if ((dc_chan == 1) || (dc_chan == 5)) { |
| 583 | ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0); |
| 584 | ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0); |
| 585 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0); |
| 586 | ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); |
| 587 | ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); |
| 588 | ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); |
| 589 | ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); |
| 590 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); |
| 591 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); |
| 592 | } else if ((dc_chan == 8) || (dc_chan == 9)) { |
| 593 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0); |
| 594 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0); |
| 595 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0); |
| 596 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0); |
| 597 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0); |
| 598 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0); |
| 599 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0); |
| 600 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0); |
| 601 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0); |
| 602 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0); |
| 603 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0); |
| 604 | ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | int ipu_chan_is_interlaced(ipu_channel_t channel) |
| 609 | { |
| 610 | if (channel == MEM_DC_SYNC) |
| 611 | return !!(__raw_readl(DC_WR_CH_CONF_1) & |
| 612 | DC_WR_CH_CONF_FIELD_MODE); |
| 613 | else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) |
| 614 | return !!(__raw_readl(DC_WR_CH_CONF_5) & |
| 615 | DC_WR_CH_CONF_FIELD_MODE); |
| 616 | return 0; |
| 617 | } |
| 618 | |
| 619 | void ipu_dp_dc_enable(ipu_channel_t channel) |
| 620 | { |
| 621 | int di; |
| 622 | uint32_t reg; |
| 623 | uint32_t dc_chan; |
| 624 | |
| 625 | if (channel == MEM_FG_SYNC) |
| 626 | dc_chan = 5; |
| 627 | if (channel == MEM_DC_SYNC) |
| 628 | dc_chan = 1; |
| 629 | else if (channel == MEM_BG_SYNC) |
| 630 | dc_chan = 5; |
| 631 | else |
| 632 | return; |
| 633 | |
| 634 | if (channel == MEM_FG_SYNC) { |
| 635 | /* Enable FG channel */ |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 636 | reg = __raw_readl(DP_COM_CONF()); |
| 637 | __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 638 | |
| 639 | reg = __raw_readl(IPU_SRM_PRI2) | 0x8; |
| 640 | __raw_writel(reg, IPU_SRM_PRI2); |
| 641 | return; |
| 642 | } |
| 643 | |
| 644 | di = g_dc_di_assignment[dc_chan]; |
| 645 | |
| 646 | /* Make sure other DC sync channel is not assigned same DI */ |
| 647 | reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); |
| 648 | if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { |
| 649 | reg &= ~DC_WR_CH_CONF_PROG_DI_ID; |
| 650 | reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; |
| 651 | __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); |
| 652 | } |
| 653 | |
| 654 | reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); |
| 655 | reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; |
| 656 | __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); |
| 657 | |
| 658 | clk_enable(g_pixel_clk[di]); |
| 659 | } |
| 660 | |
| 661 | static unsigned char dc_swap; |
| 662 | |
| 663 | void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) |
| 664 | { |
| 665 | uint32_t reg; |
| 666 | uint32_t csc; |
| 667 | uint32_t dc_chan = 0; |
| 668 | int timeout = 50; |
| 669 | |
| 670 | dc_swap = swap; |
| 671 | |
| 672 | if (channel == MEM_DC_SYNC) { |
| 673 | dc_chan = 1; |
| 674 | } else if (channel == MEM_BG_SYNC) { |
| 675 | dc_chan = 5; |
| 676 | } else if (channel == MEM_FG_SYNC) { |
| 677 | /* Disable FG channel */ |
| 678 | dc_chan = 5; |
| 679 | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 680 | reg = __raw_readl(DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 681 | csc = reg & DP_COM_CONF_CSC_DEF_MASK; |
| 682 | if (csc == DP_COM_CONF_CSC_DEF_FG) |
| 683 | reg &= ~DP_COM_CONF_CSC_DEF_MASK; |
| 684 | |
| 685 | reg &= ~DP_COM_CONF_FG_EN; |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 686 | __raw_writel(reg, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 687 | |
| 688 | reg = __raw_readl(IPU_SRM_PRI2) | 0x8; |
| 689 | __raw_writel(reg, IPU_SRM_PRI2); |
| 690 | |
| 691 | timeout = 50; |
| 692 | |
| 693 | /* |
| 694 | * Wait for DC triple buffer to empty, |
| 695 | * this check is useful for tv overlay. |
| 696 | */ |
| 697 | if (g_dc_di_assignment[dc_chan] == 0) |
| 698 | while ((__raw_readl(DC_STAT) & 0x00000002) |
| 699 | != 0x00000002) { |
| 700 | udelay(2000); |
| 701 | timeout -= 2; |
| 702 | if (timeout <= 0) |
| 703 | break; |
| 704 | } |
| 705 | else if (g_dc_di_assignment[dc_chan] == 1) |
| 706 | while ((__raw_readl(DC_STAT) & 0x00000020) |
| 707 | != 0x00000020) { |
| 708 | udelay(2000); |
| 709 | timeout -= 2; |
| 710 | if (timeout <= 0) |
| 711 | break; |
| 712 | } |
| 713 | return; |
| 714 | } else { |
| 715 | return; |
| 716 | } |
| 717 | |
| 718 | if (dc_swap) { |
| 719 | /* Swap DC channel 1 and 5 settings, and disable old dc chan */ |
| 720 | reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); |
| 721 | __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); |
| 722 | reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; |
| 723 | reg ^= DC_WR_CH_CONF_PROG_DI_ID; |
| 724 | __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); |
| 725 | } else { |
| 726 | timeout = 50; |
| 727 | |
| 728 | /* Wait for DC triple buffer to empty */ |
| 729 | if (g_dc_di_assignment[dc_chan] == 0) |
| 730 | while ((__raw_readl(DC_STAT) & 0x00000002) |
| 731 | != 0x00000002) { |
| 732 | udelay(2000); |
| 733 | timeout -= 2; |
| 734 | if (timeout <= 0) |
| 735 | break; |
| 736 | } |
| 737 | else if (g_dc_di_assignment[dc_chan] == 1) |
| 738 | while ((__raw_readl(DC_STAT) & 0x00000020) |
| 739 | != 0x00000020) { |
| 740 | udelay(2000); |
| 741 | timeout -= 2; |
| 742 | if (timeout <= 0) |
| 743 | break; |
| 744 | } |
| 745 | |
| 746 | reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); |
| 747 | reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; |
| 748 | __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); |
| 749 | |
| 750 | reg = __raw_readl(IPU_DISP_GEN); |
| 751 | if (g_dc_di_assignment[dc_chan]) |
| 752 | reg &= ~DI1_COUNTER_RELEASE; |
| 753 | else |
| 754 | reg &= ~DI0_COUNTER_RELEASE; |
| 755 | __raw_writel(reg, IPU_DISP_GEN); |
| 756 | |
| 757 | /* Clock is already off because it must be done quickly, but |
| 758 | we need to fix the ref count */ |
| 759 | clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]); |
| 760 | } |
| 761 | } |
| 762 | |
| 763 | void ipu_init_dc_mappings(void) |
| 764 | { |
| 765 | /* IPU_PIX_FMT_RGB24 */ |
| 766 | ipu_dc_map_clear(0); |
| 767 | ipu_dc_map_config(0, 0, 7, 0xFF); |
| 768 | ipu_dc_map_config(0, 1, 15, 0xFF); |
| 769 | ipu_dc_map_config(0, 2, 23, 0xFF); |
| 770 | |
| 771 | /* IPU_PIX_FMT_RGB666 */ |
| 772 | ipu_dc_map_clear(1); |
| 773 | ipu_dc_map_config(1, 0, 5, 0xFC); |
| 774 | ipu_dc_map_config(1, 1, 11, 0xFC); |
| 775 | ipu_dc_map_config(1, 2, 17, 0xFC); |
| 776 | |
| 777 | /* IPU_PIX_FMT_YUV444 */ |
| 778 | ipu_dc_map_clear(2); |
| 779 | ipu_dc_map_config(2, 0, 15, 0xFF); |
| 780 | ipu_dc_map_config(2, 1, 23, 0xFF); |
| 781 | ipu_dc_map_config(2, 2, 7, 0xFF); |
| 782 | |
| 783 | /* IPU_PIX_FMT_RGB565 */ |
| 784 | ipu_dc_map_clear(3); |
| 785 | ipu_dc_map_config(3, 0, 4, 0xF8); |
| 786 | ipu_dc_map_config(3, 1, 10, 0xFC); |
| 787 | ipu_dc_map_config(3, 2, 15, 0xF8); |
| 788 | |
| 789 | /* IPU_PIX_FMT_LVDS666 */ |
| 790 | ipu_dc_map_clear(4); |
| 791 | ipu_dc_map_config(4, 0, 5, 0xFC); |
| 792 | ipu_dc_map_config(4, 1, 13, 0xFC); |
| 793 | ipu_dc_map_config(4, 2, 21, 0xFC); |
| 794 | } |
| 795 | |
| 796 | int ipu_pixfmt_to_map(uint32_t fmt) |
| 797 | { |
| 798 | switch (fmt) { |
| 799 | case IPU_PIX_FMT_GENERIC: |
| 800 | case IPU_PIX_FMT_RGB24: |
| 801 | return 0; |
| 802 | case IPU_PIX_FMT_RGB666: |
| 803 | return 1; |
| 804 | case IPU_PIX_FMT_YUV444: |
| 805 | return 2; |
| 806 | case IPU_PIX_FMT_RGB565: |
| 807 | return 3; |
| 808 | case IPU_PIX_FMT_LVDS666: |
| 809 | return 4; |
| 810 | } |
| 811 | |
| 812 | return -1; |
| 813 | } |
| 814 | |
| 815 | /* |
| 816 | * This function is called to adapt synchronous LCD panel to IPU restriction. |
| 817 | */ |
| 818 | void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk, |
| 819 | uint16_t width, uint16_t height, |
| 820 | uint16_t h_start_width, |
| 821 | uint16_t h_end_width, |
| 822 | uint16_t v_start_width, |
| 823 | uint16_t *v_end_width) |
| 824 | { |
| 825 | if (*v_end_width < 2) { |
| 826 | uint16_t total_width = width + h_start_width + h_end_width; |
| 827 | uint16_t total_height_old = height + v_start_width + |
| 828 | (*v_end_width); |
| 829 | uint16_t total_height_new = height + v_start_width + 2; |
| 830 | *v_end_width = 2; |
| 831 | *pixel_clk = (*pixel_clk) * total_width * total_height_new / |
| 832 | (total_width * total_height_old); |
| 833 | printf("WARNING: adapt panel end blank lines\n"); |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | /* |
| 838 | * This function is called to initialize a synchronous LCD panel. |
| 839 | * |
| 840 | * @param disp The DI the panel is attached to. |
| 841 | * |
| 842 | * @param pixel_clk Desired pixel clock frequency in Hz. |
| 843 | * |
| 844 | * @param pixel_fmt Input parameter for pixel format of buffer. |
| 845 | * Pixel format is a FOURCC ASCII code. |
| 846 | * |
| 847 | * @param width The width of panel in pixels. |
| 848 | * |
| 849 | * @param height The height of panel in pixels. |
| 850 | * |
| 851 | * @param hStartWidth The number of pixel clocks between the HSYNC |
| 852 | * signal pulse and the start of valid data. |
| 853 | * |
| 854 | * @param hSyncWidth The width of the HSYNC signal in units of pixel |
| 855 | * clocks. |
| 856 | * |
| 857 | * @param hEndWidth The number of pixel clocks between the end of |
| 858 | * valid data and the HSYNC signal for next line. |
| 859 | * |
| 860 | * @param vStartWidth The number of lines between the VSYNC |
| 861 | * signal pulse and the start of valid data. |
| 862 | * |
| 863 | * @param vSyncWidth The width of the VSYNC signal in units of lines |
| 864 | * |
| 865 | * @param vEndWidth The number of lines between the end of valid |
| 866 | * data and the VSYNC signal for next frame. |
| 867 | * |
| 868 | * @param sig Bitfield of signal polarities for LCD interface. |
| 869 | * |
| 870 | * @return This function returns 0 on success or negative error code on |
| 871 | * fail. |
| 872 | */ |
| 873 | |
| 874 | int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, |
| 875 | uint16_t width, uint16_t height, |
| 876 | uint32_t pixel_fmt, |
| 877 | uint16_t h_start_width, uint16_t h_sync_width, |
| 878 | uint16_t h_end_width, uint16_t v_start_width, |
| 879 | uint16_t v_sync_width, uint16_t v_end_width, |
| 880 | uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) |
| 881 | { |
| 882 | uint32_t reg; |
| 883 | uint32_t di_gen, vsync_cnt; |
| 884 | uint32_t div, rounded_pixel_clk; |
| 885 | uint32_t h_total, v_total; |
| 886 | int map; |
| 887 | struct clk *di_parent; |
| 888 | |
| 889 | debug("panel size = %d x %d\n", width, height); |
| 890 | |
| 891 | if ((v_sync_width == 0) || (h_sync_width == 0)) |
| 892 | return EINVAL; |
| 893 | |
| 894 | adapt_panel_to_ipu_restricitions(&pixel_clk, width, height, |
| 895 | h_start_width, h_end_width, |
| 896 | v_start_width, &v_end_width); |
| 897 | h_total = width + h_sync_width + h_start_width + h_end_width; |
| 898 | v_total = height + v_sync_width + v_start_width + v_end_width; |
| 899 | |
| 900 | /* Init clocking */ |
| 901 | debug("pixel clk = %d\n", pixel_clk); |
| 902 | |
| 903 | if (sig.ext_clk) { |
| 904 | if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ |
| 905 | /* |
| 906 | * Set the PLL to be an even multiple |
| 907 | * of the pixel clock. |
| 908 | */ |
| 909 | if ((clk_get_usecount(g_pixel_clk[0]) == 0) && |
| 910 | (clk_get_usecount(g_pixel_clk[1]) == 0)) { |
| 911 | di_parent = clk_get_parent(g_di_clk[disp]); |
| 912 | rounded_pixel_clk = |
| 913 | clk_round_rate(g_pixel_clk[disp], |
| 914 | pixel_clk); |
| 915 | div = clk_get_rate(di_parent) / |
| 916 | rounded_pixel_clk; |
| 917 | if (div % 2) |
| 918 | div++; |
| 919 | if (clk_get_rate(di_parent) != div * |
| 920 | rounded_pixel_clk) |
| 921 | clk_set_rate(di_parent, |
| 922 | div * rounded_pixel_clk); |
| 923 | udelay(10000); |
| 924 | clk_set_rate(g_di_clk[disp], |
| 925 | 2 * rounded_pixel_clk); |
| 926 | udelay(10000); |
| 927 | } |
| 928 | } |
Eric Nelson | 5018c55 | 2012-05-31 07:24:02 +0000 | [diff] [blame] | 929 | clk_set_parent(g_pixel_clk[disp], g_ldb_clk); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 930 | } else { |
| 931 | if (clk_get_usecount(g_pixel_clk[disp]) != 0) |
| 932 | clk_set_parent(g_pixel_clk[disp], g_ipu_clk); |
| 933 | } |
| 934 | rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); |
| 935 | clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); |
| 936 | udelay(5000); |
| 937 | /* Get integer portion of divider */ |
| 938 | div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / |
| 939 | rounded_pixel_clk; |
| 940 | |
| 941 | ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); |
| 942 | ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); |
| 943 | |
| 944 | map = ipu_pixfmt_to_map(pixel_fmt); |
| 945 | if (map < 0) { |
| 946 | debug("IPU_DISP: No MAP\n"); |
| 947 | return -EINVAL; |
| 948 | } |
| 949 | |
| 950 | di_gen = __raw_readl(DI_GENERAL(disp)); |
| 951 | |
| 952 | if (sig.interlaced) { |
| 953 | /* Setup internal HSYNC waveform */ |
| 954 | ipu_di_sync_config( |
| 955 | disp, /* display */ |
| 956 | 1, /* counter */ |
| 957 | h_total / 2 - 1,/* run count */ |
| 958 | DI_SYNC_CLK, /* run_resolution */ |
| 959 | 0, /* offset */ |
| 960 | DI_SYNC_NONE, /* offset resolution */ |
| 961 | 0, /* repeat count */ |
| 962 | DI_SYNC_NONE, /* CNT_CLR_SEL */ |
| 963 | 0, /* CNT_POLARITY_GEN_EN */ |
| 964 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 965 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 966 | 0, /* COUNT UP */ |
| 967 | 0 /* COUNT DOWN */ |
| 968 | ); |
| 969 | |
| 970 | /* Field 1 VSYNC waveform */ |
| 971 | ipu_di_sync_config( |
| 972 | disp, /* display */ |
| 973 | 2, /* counter */ |
| 974 | h_total - 1, /* run count */ |
| 975 | DI_SYNC_CLK, /* run_resolution */ |
| 976 | 0, /* offset */ |
| 977 | DI_SYNC_NONE, /* offset resolution */ |
| 978 | 0, /* repeat count */ |
| 979 | DI_SYNC_NONE, /* CNT_CLR_SEL */ |
| 980 | 0, /* CNT_POLARITY_GEN_EN */ |
| 981 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 982 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 983 | 0, /* COUNT UP */ |
| 984 | 4 /* COUNT DOWN */ |
| 985 | ); |
| 986 | |
| 987 | /* Setup internal HSYNC waveform */ |
| 988 | ipu_di_sync_config( |
| 989 | disp, /* display */ |
| 990 | 3, /* counter */ |
| 991 | v_total * 2 - 1,/* run count */ |
| 992 | DI_SYNC_INT_HSYNC, /* run_resolution */ |
| 993 | 1, /* offset */ |
| 994 | DI_SYNC_INT_HSYNC, /* offset resolution */ |
| 995 | 0, /* repeat count */ |
| 996 | DI_SYNC_NONE, /* CNT_CLR_SEL */ |
| 997 | 0, /* CNT_POLARITY_GEN_EN */ |
| 998 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 999 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1000 | 0, /* COUNT UP */ |
| 1001 | 4 /* COUNT DOWN */ |
| 1002 | ); |
| 1003 | |
| 1004 | /* Active Field ? */ |
| 1005 | ipu_di_sync_config( |
| 1006 | disp, /* display */ |
| 1007 | 4, /* counter */ |
| 1008 | v_total / 2 - 1,/* run count */ |
| 1009 | DI_SYNC_HSYNC, /* run_resolution */ |
| 1010 | v_start_width, /* offset */ |
| 1011 | DI_SYNC_HSYNC, /* offset resolution */ |
| 1012 | 2, /* repeat count */ |
| 1013 | DI_SYNC_VSYNC, /* CNT_CLR_SEL */ |
| 1014 | 0, /* CNT_POLARITY_GEN_EN */ |
| 1015 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 1016 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1017 | 0, /* COUNT UP */ |
| 1018 | 0 /* COUNT DOWN */ |
| 1019 | ); |
| 1020 | |
| 1021 | /* Active Line */ |
| 1022 | ipu_di_sync_config( |
| 1023 | disp, /* display */ |
| 1024 | 5, /* counter */ |
| 1025 | 0, /* run count */ |
| 1026 | DI_SYNC_HSYNC, /* run_resolution */ |
| 1027 | 0, /* offset */ |
| 1028 | DI_SYNC_NONE, /* offset resolution */ |
| 1029 | height / 2, /* repeat count */ |
| 1030 | 4, /* CNT_CLR_SEL */ |
| 1031 | 0, /* CNT_POLARITY_GEN_EN */ |
| 1032 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 1033 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1034 | 0, /* COUNT UP */ |
| 1035 | 0 /* COUNT DOWN */ |
| 1036 | ); |
| 1037 | |
| 1038 | /* Field 0 VSYNC waveform */ |
| 1039 | ipu_di_sync_config( |
| 1040 | disp, /* display */ |
| 1041 | 6, /* counter */ |
| 1042 | v_total - 1, /* run count */ |
| 1043 | DI_SYNC_HSYNC, /* run_resolution */ |
| 1044 | 0, /* offset */ |
| 1045 | DI_SYNC_NONE, /* offset resolution */ |
| 1046 | 0, /* repeat count */ |
| 1047 | DI_SYNC_NONE, /* CNT_CLR_SEL */ |
| 1048 | 0, /* CNT_POLARITY_GEN_EN */ |
| 1049 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 1050 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1051 | 0, /* COUNT UP */ |
| 1052 | 0 /* COUNT DOWN */ |
| 1053 | ); |
| 1054 | |
| 1055 | /* DC VSYNC waveform */ |
| 1056 | vsync_cnt = 7; |
| 1057 | ipu_di_sync_config( |
| 1058 | disp, /* display */ |
| 1059 | 7, /* counter */ |
| 1060 | v_total / 2 - 1,/* run count */ |
| 1061 | DI_SYNC_HSYNC, /* run_resolution */ |
| 1062 | 9, /* offset */ |
| 1063 | DI_SYNC_HSYNC, /* offset resolution */ |
| 1064 | 2, /* repeat count */ |
| 1065 | DI_SYNC_VSYNC, /* CNT_CLR_SEL */ |
| 1066 | 0, /* CNT_POLARITY_GEN_EN */ |
| 1067 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 1068 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1069 | 0, /* COUNT UP */ |
| 1070 | 0 /* COUNT DOWN */ |
| 1071 | ); |
| 1072 | |
| 1073 | /* active pixel waveform */ |
| 1074 | ipu_di_sync_config( |
| 1075 | disp, /* display */ |
| 1076 | 8, /* counter */ |
| 1077 | 0, /* run count */ |
| 1078 | DI_SYNC_CLK, /* run_resolution */ |
| 1079 | h_start_width, /* offset */ |
| 1080 | DI_SYNC_CLK, /* offset resolution */ |
| 1081 | width, /* repeat count */ |
| 1082 | 5, /* CNT_CLR_SEL */ |
| 1083 | 0, /* CNT_POLARITY_GEN_EN */ |
| 1084 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 1085 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1086 | 0, /* COUNT UP */ |
| 1087 | 0 /* COUNT DOWN */ |
| 1088 | ); |
| 1089 | |
| 1090 | ipu_di_sync_config( |
| 1091 | disp, /* display */ |
| 1092 | 9, /* counter */ |
| 1093 | v_total - 1, /* run count */ |
| 1094 | DI_SYNC_INT_HSYNC,/* run_resolution */ |
| 1095 | v_total / 2, /* offset */ |
| 1096 | DI_SYNC_INT_HSYNC,/* offset resolution */ |
| 1097 | 0, /* repeat count */ |
| 1098 | DI_SYNC_HSYNC, /* CNT_CLR_SEL */ |
| 1099 | 0, /* CNT_POLARITY_GEN_EN */ |
| 1100 | DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ |
| 1101 | DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ |
| 1102 | 0, /* COUNT UP */ |
| 1103 | 4 /* COUNT DOWN */ |
| 1104 | ); |
| 1105 | |
| 1106 | /* set gentime select and tag sel */ |
| 1107 | reg = __raw_readl(DI_SW_GEN1(disp, 9)); |
| 1108 | reg &= 0x1FFFFFFF; |
| 1109 | reg |= (3 - 1)<<29 | 0x00008000; |
| 1110 | __raw_writel(reg, DI_SW_GEN1(disp, 9)); |
| 1111 | |
| 1112 | __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); |
| 1113 | |
| 1114 | /* set y_sel = 1 */ |
| 1115 | di_gen |= 0x10000000; |
| 1116 | di_gen |= DI_GEN_POLARITY_5; |
| 1117 | di_gen |= DI_GEN_POLARITY_8; |
| 1118 | } else { |
| 1119 | /* Setup internal HSYNC waveform */ |
| 1120 | ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, |
| 1121 | 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, |
| 1122 | 0, DI_SYNC_NONE, |
| 1123 | DI_SYNC_NONE, 0, 0); |
| 1124 | |
| 1125 | /* Setup external (delayed) HSYNC waveform */ |
| 1126 | ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, |
| 1127 | DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, |
| 1128 | 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, |
| 1129 | DI_SYNC_CLK, 0, h_sync_width * 2); |
| 1130 | /* Setup VSYNC waveform */ |
| 1131 | vsync_cnt = DI_SYNC_VSYNC; |
| 1132 | ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, |
| 1133 | DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0, |
| 1134 | DI_SYNC_NONE, 1, DI_SYNC_NONE, |
| 1135 | DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); |
| 1136 | __raw_writel(v_total - 1, DI_SCR_CONF(disp)); |
| 1137 | |
| 1138 | /* Setup active data waveform to sync with DC */ |
| 1139 | ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC, |
| 1140 | v_sync_width + v_start_width, DI_SYNC_HSYNC, |
| 1141 | height, |
| 1142 | DI_SYNC_VSYNC, 0, DI_SYNC_NONE, |
| 1143 | DI_SYNC_NONE, 0, 0); |
| 1144 | ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, |
| 1145 | h_sync_width + h_start_width, DI_SYNC_CLK, |
| 1146 | width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, |
| 1147 | 0); |
| 1148 | |
| 1149 | /* reset all unused counters */ |
| 1150 | __raw_writel(0, DI_SW_GEN0(disp, 6)); |
| 1151 | __raw_writel(0, DI_SW_GEN1(disp, 6)); |
| 1152 | __raw_writel(0, DI_SW_GEN0(disp, 7)); |
| 1153 | __raw_writel(0, DI_SW_GEN1(disp, 7)); |
| 1154 | __raw_writel(0, DI_SW_GEN0(disp, 8)); |
| 1155 | __raw_writel(0, DI_SW_GEN1(disp, 8)); |
| 1156 | __raw_writel(0, DI_SW_GEN0(disp, 9)); |
| 1157 | __raw_writel(0, DI_SW_GEN1(disp, 9)); |
| 1158 | |
| 1159 | reg = __raw_readl(DI_STP_REP(disp, 6)); |
| 1160 | reg &= 0x0000FFFF; |
| 1161 | __raw_writel(reg, DI_STP_REP(disp, 6)); |
| 1162 | __raw_writel(0, DI_STP_REP(disp, 7)); |
| 1163 | __raw_writel(0, DI_STP_REP(disp, 9)); |
| 1164 | |
| 1165 | /* Init template microcode */ |
| 1166 | if (disp) { |
| 1167 | ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); |
| 1168 | ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); |
| 1169 | ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); |
| 1170 | } else { |
| 1171 | ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5); |
| 1172 | ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5); |
| 1173 | ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5); |
| 1174 | } |
| 1175 | |
| 1176 | if (sig.Hsync_pol) |
| 1177 | di_gen |= DI_GEN_POLARITY_2; |
| 1178 | if (sig.Vsync_pol) |
| 1179 | di_gen |= DI_GEN_POLARITY_3; |
| 1180 | |
Fabio Estevam | d6e427a | 2013-10-29 15:46:21 -0200 | [diff] [blame] | 1181 | if (!sig.clk_pol) |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1182 | di_gen |= DI_GEN_POL_CLK; |
| 1183 | |
| 1184 | } |
| 1185 | |
| 1186 | __raw_writel(di_gen, DI_GENERAL(disp)); |
| 1187 | |
| 1188 | __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | |
| 1189 | 0x00000002, DI_SYNC_AS_GEN(disp)); |
| 1190 | |
| 1191 | reg = __raw_readl(DI_POL(disp)); |
| 1192 | reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); |
| 1193 | if (sig.enable_pol) |
| 1194 | reg |= DI_POL_DRDY_POLARITY_15; |
| 1195 | if (sig.data_pol) |
| 1196 | reg |= DI_POL_DRDY_DATA_POLARITY; |
| 1197 | __raw_writel(reg, DI_POL(disp)); |
| 1198 | |
| 1199 | __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp))); |
| 1200 | |
| 1201 | return 0; |
| 1202 | } |
| 1203 | |
| 1204 | /* |
| 1205 | * This function sets the foreground and background plane global alpha blending |
| 1206 | * modes. This function also sets the DP graphic plane according to the |
| 1207 | * parameter of IPUv3 DP channel. |
| 1208 | * |
| 1209 | * @param channel IPUv3 DP channel |
| 1210 | * |
| 1211 | * @param enable Boolean to enable or disable global alpha |
| 1212 | * blending. If disabled, local blending is used. |
| 1213 | * |
| 1214 | * @param alpha Global alpha value. |
| 1215 | * |
| 1216 | * @return Returns 0 on success or negative error code on fail |
| 1217 | */ |
| 1218 | int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, |
| 1219 | uint8_t alpha) |
| 1220 | { |
| 1221 | uint32_t reg; |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1222 | |
| 1223 | unsigned char bg_chan; |
| 1224 | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1225 | if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || |
| 1226 | (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || |
| 1227 | (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1228 | return -EINVAL; |
| 1229 | |
| 1230 | if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 || |
| 1231 | channel == MEM_BG_ASYNC1) |
| 1232 | bg_chan = 1; |
| 1233 | else |
| 1234 | bg_chan = 0; |
| 1235 | |
| 1236 | if (!g_ipu_clk_enabled) |
| 1237 | clk_enable(g_ipu_clk); |
| 1238 | |
| 1239 | if (bg_chan) { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1240 | reg = __raw_readl(DP_COM_CONF()); |
| 1241 | __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1242 | } else { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1243 | reg = __raw_readl(DP_COM_CONF()); |
| 1244 | __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1245 | } |
| 1246 | |
| 1247 | if (enable) { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1248 | reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL; |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1249 | __raw_writel(reg | ((uint32_t) alpha << 24), |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1250 | DP_GRAPH_WIND_CTRL()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1251 | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1252 | reg = __raw_readl(DP_COM_CONF()); |
| 1253 | __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1254 | } else { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1255 | reg = __raw_readl(DP_COM_CONF()); |
| 1256 | __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1257 | } |
| 1258 | |
| 1259 | reg = __raw_readl(IPU_SRM_PRI2) | 0x8; |
| 1260 | __raw_writel(reg, IPU_SRM_PRI2); |
| 1261 | |
| 1262 | if (!g_ipu_clk_enabled) |
| 1263 | clk_disable(g_ipu_clk); |
| 1264 | |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
| 1268 | /* |
| 1269 | * This function sets the transparent color key for SDC graphic plane. |
| 1270 | * |
| 1271 | * @param channel Input parameter for the logical channel ID. |
| 1272 | * |
| 1273 | * @param enable Boolean to enable or disable color key |
| 1274 | * |
| 1275 | * @param colorKey 24-bit RGB color for transparent color key. |
| 1276 | * |
| 1277 | * @return Returns 0 on success or negative error code on fail |
| 1278 | */ |
| 1279 | int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, |
| 1280 | uint32_t color_key) |
| 1281 | { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1282 | uint32_t reg; |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1283 | int y, u, v; |
| 1284 | int red, green, blue; |
| 1285 | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1286 | if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || |
| 1287 | (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || |
| 1288 | (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1289 | return -EINVAL; |
| 1290 | |
| 1291 | if (!g_ipu_clk_enabled) |
| 1292 | clk_enable(g_ipu_clk); |
| 1293 | |
| 1294 | color_key_4rgb = 1; |
| 1295 | /* Transform color key from rgb to yuv if CSC is enabled */ |
| 1296 | if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || |
| 1297 | ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || |
| 1298 | ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || |
| 1299 | ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) { |
| 1300 | |
| 1301 | debug("color key 0x%x need change to yuv fmt\n", color_key); |
| 1302 | |
| 1303 | red = (color_key >> 16) & 0xFF; |
| 1304 | green = (color_key >> 8) & 0xFF; |
| 1305 | blue = color_key & 0xFF; |
| 1306 | |
| 1307 | y = rgb_to_yuv(0, red, green, blue); |
| 1308 | u = rgb_to_yuv(1, red, green, blue); |
| 1309 | v = rgb_to_yuv(2, red, green, blue); |
| 1310 | color_key = (y << 16) | (u << 8) | v; |
| 1311 | |
| 1312 | color_key_4rgb = 0; |
| 1313 | |
| 1314 | debug("color key change to yuv fmt 0x%x\n", color_key); |
| 1315 | } |
| 1316 | |
| 1317 | if (enable) { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1318 | reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; |
| 1319 | __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1320 | |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1321 | reg = __raw_readl(DP_COM_CONF()); |
| 1322 | __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1323 | } else { |
Marek Vasut | c6b9533 | 2011-09-26 02:26:05 +0200 | [diff] [blame] | 1324 | reg = __raw_readl(DP_COM_CONF()); |
| 1325 | __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF()); |
Stefano Babic | ed5939d | 2010-10-13 12:16:35 +0200 | [diff] [blame] | 1326 | } |
| 1327 | |
| 1328 | reg = __raw_readl(IPU_SRM_PRI2) | 0x8; |
| 1329 | __raw_writel(reg, IPU_SRM_PRI2); |
| 1330 | |
| 1331 | if (!g_ipu_clk_enabled) |
| 1332 | clk_disable(g_ipu_clk); |
| 1333 | |
| 1334 | return 0; |
| 1335 | } |