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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiewb859ef12007-08-16 19:23:50 -05002/*
3 *
Alison Wangd132fe62012-03-26 21:49:06 +00004 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewb859ef12007-08-16 19:23:50 -05005 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewb859ef12007-08-16 19:23:50 -05006 */
7
8/* CPU specific interrupt routine */
9#include <common.h>
Simon Glass9b61c7c2019-11-14 12:57:41 -070010#include <irq_func.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -050011#include <asm/immap.h>
Alison Wangd132fe62012-03-26 21:49:06 +000012#include <asm/io.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -050013
14int interrupt_init(void)
15{
Tom Rini364d0022023-01-10 11:19:45 -050016 int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
TsiChungLiewb859ef12007-08-16 19:23:50 -050017
18 /* Make sure all interrupts are disabled */
Alison Wangd132fe62012-03-26 21:49:06 +000019 setbits_be32(&intp->imrl0, 0x1);
TsiChungLiewb859ef12007-08-16 19:23:50 -050020
21 enable_interrupts();
22 return 0;
23}
24
Angelo Dureghello49becce2023-02-25 23:25:26 +010025#if defined(CFG_MCFTMR)
TsiChungLiewb859ef12007-08-16 19:23:50 -050026void dtimer_intr_setup(void)
27{
Tom Rini364d0022023-01-10 11:19:45 -050028 int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
TsiChungLiewb859ef12007-08-16 19:23:50 -050029
Tom Rini364d0022023-01-10 11:19:45 -050030 out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
Alison Wangd132fe62012-03-26 21:49:06 +000031 clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
Tom Rini364d0022023-01-10 11:19:45 -050032 clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
TsiChungLiewb859ef12007-08-16 19:23:50 -050033}
34#endif