| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Steve Rae | 45f2c70 | 2016-06-02 15:10:56 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2013 Broadcom Corporation. |
| Steve Rae | 45f2c70 | 2016-06-02 15:10:56 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __ARCH_BCM235XX_SYSMAP_H |
| 7 | |
| 8 | #define BSC1_BASE_ADDR 0x3e016000 |
| 9 | #define BSC2_BASE_ADDR 0x3e017000 |
| 10 | #define BSC3_BASE_ADDR 0x3e018000 |
| 11 | #define GPIO2_BASE_ADDR 0x35003000 |
| 12 | #define HSOTG_BASE_ADDR 0x3f120000 |
| 13 | #define HSOTG_CTRL_BASE_ADDR 0x3f130000 |
| 14 | #define KONA_MST_CLK_BASE_ADDR 0x3f001000 |
| 15 | #define KONA_SLV_CLK_BASE_ADDR 0x3e011000 |
| 16 | #define PMU_BSC_BASE_ADDR 0x3500d000 |
| 17 | #define SDIO1_BASE_ADDR 0x3f180000 |
| 18 | #define SDIO2_BASE_ADDR 0x3f190000 |
| 19 | #define SDIO3_BASE_ADDR 0x3f1a0000 |
| 20 | #define SDIO4_BASE_ADDR 0x3f1b0000 |
| 21 | #define TIMER_BASE_ADDR 0x3e00d000 |
| 22 | |
| 23 | #define HSOTG_DCTL_OFFSET 0x00000804 |
| 24 | #define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 |
| 25 | |
| 26 | #define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 |
| 27 | #define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 |
| 28 | #define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 |
| 29 | |
| 30 | #endif |