Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 190bddf0dbae23f4d9352bc2a5ef48752b38b710 / . / arch / arm / dts / mt7988.dtsi
blob: ddd629e8c99d50a25cc748fc5ed6a6e05465f513 [file] [log] [blame]
developerf596c1a2023-07-19 17:17:49 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7988-clk.h>
10#include <dt-bindings/reset/mt7988-reset.h>
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14 compatible = "mediatek,mt7988-rfb";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a73";
26 reg = <0x0>;
27 mediatek,hwver = <&hwver>;
28 };
29
30 cpu1: cpu@1 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a73";
33 reg = <0x1>;
34 mediatek,hwver = <&hwver>;
35 };
36
37 cpu2: cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a73";
40 reg = <0x2>;
41 mediatek,hwver = <&hwver>;
42 };
43
44 cpu3: cpu@3 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a73";
47 reg = <0x3>;
48 mediatek,hwver = <&hwver>;
49 };
50 };
51
52 system_clk: dummy40m {
53 compatible = "fixed-clock";
54 clock-frequency = <40000000>;
55 #clock-cells = <0>;
56 };
57
58 spi_clk: dummy208m {
59 compatible = "fixed-clock";
60 clock-frequency = <208000000>;
61 #clock-cells = <0>;
62 };
63
64 hwver: hwver {
65 compatible = "mediatek,hwver", "syscon";
66 reg = <0 0x8000000 0 0x1000>;
67 };
68
69 timer {
70 compatible = "arm,armv8-timer";
71 interrupt-parent = <&gic>;
72 clock-frequency = <13000000>;
73 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
74 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
75 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
76 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
77 };
78
79 watchdog: watchdog@1001c000 {
80 compatible = "mediatek,mt7622-wdt",
81 "mediatek,mt6589-wdt",
82 "syscon";
83 reg = <0 0x1001c000 0 0x1000>;
84 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
85 #reset-cells = <1>;
86 };
87
88 gic: interrupt-controller@c000000 {
89 compatible = "arm,gic-v3";
90 #interrupt-cells = <3>;
91 interrupt-parent = <&gic>;
92 interrupt-controller;
93 reg = <0 0x0c000000 0 0x40000>, /* GICD */
94 <0 0x0c080000 0 0x200000>; /* GICR */
95 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
96 };
97
98 infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
99 compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
100 reg = <0 0x10001000 0 0x1000>;
101 clock-parent = <&infracfg_ao>;
102 #clock-cells = <1>;
103 };
104
105 apmixedsys: apmixedsys@1001e000 {
106 compatible = "mediatek,mt7988-fixed-plls", "syscon";
107 reg = <0 0x1001e000 0 0x1000>;
108 #clock-cells = <1>;
109 };
110
111 topckgen: topckgen@1001b000 {
112 compatible = "mediatek,mt7988-topckgen", "syscon";
113 reg = <0 0x1001b000 0 0x1000>;
114 clock-parent = <&apmixedsys>;
115 #clock-cells = <1>;
116 };
117
118 pinctrl: pinctrl@1001f000 {
119 compatible = "mediatek,mt7988-pinctrl";
120 reg = <0 0x1001f000 0 0x1000>,
121 <0 0x11c10000 0 0x1000>,
122 <0 0x11d00000 0 0x1000>,
123 <0 0x11d20000 0 0x1000>,
124 <0 0x11e00000 0 0x1000>,
125 <0 0x11f00000 0 0x1000>,
126 <0 0x1000b000 0 0x1000>;
127 reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
128 "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
129 "eint";
130 gpio: gpio-controller {
131 gpio-controller;
132 #gpio-cells = <2>;
133 };
134 };
135
136 sgmiisys0: syscon@10060000 {
137 compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
138 reg = <0 0x10060000 0 0x1000>;
139 clock-parent = <&topckgen>;
140 #clock-cells = <1>;
141 };
142
143 sgmiisys1: syscon@10070000 {
144 compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
145 reg = <0 0x10070000 0 0x1000>;
146 clock-parent = <&topckgen>;
147 #clock-cells = <1>;
148 };
149
150 usxgmiisys0: syscon@10080000 {
151 compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
152 reg = <0 0x10080000 0 0x1000>;
153 clock-parent = <&topckgen>;
154 #clock-cells = <1>;
155 };
156
157 usxgmiisys1: syscon@10081000 {
158 compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
159 reg = <0 0x10081000 0 0x1000>;
160 clock-parent = <&topckgen>;
161 #clock-cells = <1>;
162 };
163
164 xfi_pextp0: syscon@11f20000 {
165 compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
166 reg = <0 0x11f20000 0 0x10000>;
167 clock-parent = <&topckgen>;
168 #clock-cells = <1>;
169 };
170
171 xfi_pextp1: syscon@11f30000 {
172 compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
173 reg = <0 0x11f30000 0 0x10000>;
174 clock-parent = <&topckgen>;
175 #clock-cells = <1>;
176 };
177
178 xfi_pll: syscon@11f40000 {
179 compatible = "mediatek,mt7988-xfi_pll", "syscon";
180 reg = <0 0x11f40000 0 0x1000>;
181 clock-parent = <&topckgen>;
182 #clock-cells = <1>;
183 };
184
185 topmisc: topmisc@11d10000 {
186 compatible = "mediatek,mt7988-topmisc", "syscon",
187 "mediatek,mt7988-power-controller";
188 reg = <0 0x11d10000 0 0x10000>;
189 clock-parent = <&topckgen>;
190 #clock-cells = <1>;
191 };
192
193 infracfg_ao: infracfg@10001000 {
194 compatible = "mediatek,mt7988-infracfg", "syscon";
195 reg = <0 0x10001000 0 0x1000>;
196 clock-parent = <&topckgen>;
197 #clock-cells = <1>;
198 };
199
200 uart0: serial@11000000 {
201 compatible = "mediatek,hsuart";
202 reg = <0 0x11000000 0 0x100>;
203 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
205 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
206 <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
207 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
208 <&infracfg_ao CK_INFRA_UART_O0>;
209 status = "disabled";
210 };
211
212 uart1: serial@11000100 {
213 compatible = "mediatek,hsuart";
214 reg = <0 0x11000100 0 0x100>;
215 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
217 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
218 <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
219 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
220 <&infracfg_ao CK_INFRA_UART_O1>;
221 status = "disabled";
222 };
223
224 uart2: serial@11000200 {
225 compatible = "mediatek,hsuart";
226 reg = <0 0x11000200 0 0x100>;
227 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
229 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
230 <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
231 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
232 <&infracfg_ao CK_INFRA_UART_O2>;
233 status = "disabled";
234 };
235
236 i2c0: i2c@11003000 {
237 compatible = "mediatek,mt7988-i2c",
238 "mediatek,mt7981-i2c";
239 reg = <0 0x11003000 0 0x1000>,
240 <0 0x10217080 0 0x80>;
241 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
242 clock-div = <1>;
243 clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
244 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
245 clock-names = "main", "dma";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
251 i2c1: i2c@11004000 {
252 compatible = "mediatek,mt7988-i2c",
253 "mediatek,mt7981-i2c";
254 reg = <0 0x11004000 0 0x1000>,
255 <0 0x10217100 0 0x80>;
256 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
257 clock-div = <1>;
258 clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
259 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
260 clock-names = "main", "dma";
261 #address-cells = <1>;
262 #size-cells = <0>;
263 status = "disabled";
264 };
265
266 i2c2: i2c@11005000 {
267 compatible = "mediatek,mt7988-i2c",
268 "mediatek,mt7981-i2c";
269 reg = <0 0x11005000 0 0x1000>,
270 <0 0x10217180 0 0x80>;
271 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
272 clock-div = <1>;
273 clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
274 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
275 clock-names = "main", "dma";
276 #address-cells = <1>;
277 #size-cells = <0>;
278 status = "disabled";
279 };
280
281 pwm: pwm@10048000 {
282 compatible = "mediatek,mt7988-pwm";
283 reg = <0 0x10048000 0 0x1000>;
284 #pwm-cells = <2>;
285 clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
286 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
287 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
288 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
289 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
290 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
291 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
292 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
293 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
294 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
295 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
296 "pwm4","pwm5","pwm6","pwm7","pwm8";
297 status = "disabled";
298 };
299
300 snand: snand@11001000 {
301 compatible = "mediatek,mt7988-snand",
302 "mediatek,mt7986-snand";
303 reg = <0 0x11001000 0 0x1000>,
304 <0 0x11002000 0 0x1000>;
305 reg-names = "nfi", "ecc";
306 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&infracfg_ao CK_INFRA_SPINFI>,
308 <&infracfg_ao CK_INFRA_NFI>,
309 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
310 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
311 assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
312 <&topckgen CK_TOP_NFI1X_SEL>;
313 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
314 <&topckgen CK_TOP_CB_M_D8>;
315 status = "disabled";
316 };
317
318 spi0: spi@1100a000 {
319 compatible = "mediatek,ipm-spi";
320 reg = <0 0x11007000 0 0x100>;
321 clocks = <&spi_clk>,
322 <&spi_clk>;
323 clock-names = "sel-clk", "spi-clk";
324 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
325 status = "disabled";
326 };
327
328 spi1: spi@1100b000 {
329 compatible = "mediatek,ipm-spi";
330 reg = <0 0x11008000 0 0x100>;
331 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
332 status = "disabled";
333 };
334
335 spi2: spi@11009000 {
336 compatible = "mediatek,ipm-spi";
337 reg = <0 0x11009000 0 0x100>;
338 clocks = <&spi_clk>,
339 <&spi_clk>;
340 clock-names = "sel-clk", "spi-clk";
341 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
342 status = "disabled";
343 };
344
345 mmc0: mmc@11230000 {
346 compatible = "mediatek,mt7988-mmc",
347 "mediatek,mt7986-mmc";
348 reg = <0 0x11230000 0 0x1000>;
349 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
351 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
352 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
353 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
354 clock-names = "source", "hclk", "source_cg", "axi_cg";
355 status = "disabled";
356 };
357
358 ethdma: syscon@15000000 {
359 compatible = "mediatek,mt7988-ethdma", "syscon";
360 reg = <0 0x15000000 0 0x20000>;
361 clock-parent = <&topckgen>;
362 #clock-cells = <1>;
363 #reset-cells = <1>;
364 };
365
366 ethwarp: syscon@15031000 {
367 compatible = "mediatek,mt7988-ethwarp", "syscon";
368 reg = <0 0x15031000 0 0x1000>;
369 clock-parent = <&topckgen>;
370 #clock-cells = <1>;
371 #reset-cells = <1>;
372 };
373
374 eth: ethernet@15100000 {
375 compatible = "mediatek,mt7988-eth", "syscon";
376 reg = <0 0x15100000 0 0x20000>;
377 mediatek,ethsys = <&ethdma>;
378 mediatek,sgmiisys = <&sgmiisys0>;
379 mediatek,usxgmiisys = <&usxgmiisys0>;
380 mediatek,xfi_pextp = <&xfi_pextp0>;
381 mediatek,xfi_pll = <&xfi_pll>;
382 mediatek,infracfg = <&topmisc>;
383 mediatek,toprgu = <&watchdog>;
384 resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
385 reset-names = "fe", "mcm";
386 #address-cells = <1>;
387 #size-cells = <0>;
388 mediatek,mcm;
389 status = "disabled";
390 };
391};