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git01.mediatek.com / filogic / uboot / 18f51ec8336a72ac75e6a01ac496d84764768bc3 / . / drivers / firmware / ti_sci_static_data.h
blob: 9662bd95f28351e19fdaaafc45686cd62abf6c41 [file] [log] [blame]
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]4 *
5 */
6
7#ifndef __TI_SCI_STATIC_DATA_H
8#define __TI_SCI_STATIC_DATA_H
9
10struct ti_sci_resource_static_data {
11 u32 dev_id;
12 u16 range_start;
13 u16 range_num;
14 u8 subtype;
15};
16
17#if IS_ENABLED(CONFIG_K3_DM_FW)
18
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]19#if IS_ENABLED(CONFIG_SOC_K3_J721E)
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]20static struct ti_sci_resource_static_data rm_static_data[] = {
21 /* Free rings */
22 {
23 .dev_id = 235,
24 .subtype = 1,
25 .range_start = 124,
26 .range_num = 32,
27 },
28 /* TX channels */
29 {
30 .dev_id = 236,
31 .subtype = 13,
32 .range_start = 6,
33 .range_num = 2,
34 },
35 /* RX channels */
36 {
37 .dev_id = 236,
38 .subtype = 10,
39 .range_start = 6,
40 .range_num = 2,
41 },
42 /* RX Free flows */
43 {
44 .dev_id = 236,
45 .subtype = 0,
46 .range_start = 60,
47 .range_num = 8,
48 },
49 { },
50};
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]51#endif /* CONFIG_SOC_K3_J721E */
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]52
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]53#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]54static struct ti_sci_resource_static_data rm_static_data[] = {
55 /* Free rings */
56 {
David Huang7bee6e12022-01-25 20:56:32 +0530[diff] [blame]57 .dev_id = 272,
58 .subtype = 1,
59 .range_start = 180,
60 .range_num = 32,
61 },
62 /* TX channels */
63 {
64 .dev_id = 273,
65 .subtype = 13,
66 .range_start = 12,
67 .range_num = 2,
68 },
69 /* RX channels */
70 {
71 .dev_id = 273,
72 .subtype = 10,
73 .range_start = 12,
74 .range_num = 2,
75 },
76 /* RX Free flows */
77 {
78 .dev_id = 273,
79 .subtype = 0,
80 .range_start = 80,
81 .range_num = 8,
82 },
83 { },
84};
Vignesh Raghavendra818c9392022-06-15 19:33:05 +0530[diff] [blame]85#endif /* CONFIG_SOC_K3_J721S2 */
David Huang7bee6e12022-01-25 20:56:32 +0530[diff] [blame]86
Hari Nagalla18f51ec2024-03-12 15:20:26 -0500[diff] [blame^]87#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
88 IS_ENABLED(CONFIG_SOC_K3_AM62P5)
Vignesh Raghavendra878fe832022-05-25 13:38:45 +0530[diff] [blame]89static struct ti_sci_resource_static_data rm_static_data[] = {
90 /* BC channels */
91 {
92 .dev_id = 26,
93 .subtype = 32,
94 .range_start = 18,
95 .range_num = 2,
96 },
97 { },
98};
Hari Nagalla18f51ec2024-03-12 15:20:26 -0500[diff] [blame^]99#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || CONFIG_SOC_K3_AM62P5 */
Vignesh Raghavendra878fe832022-05-25 13:38:45 +0530[diff] [blame]100
Apurva Nandan7a25c302024-02-24 01:51:45 +0530[diff] [blame]101#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
102static struct ti_sci_resource_static_data rm_static_data[] = {
103 /* Free rings */
104 {
105 .dev_id = 328,
106 .subtype = 1,
107 .range_start = 208,
108 .range_num = 32,
109 },
110 /* TX channels */
111 {
112 .dev_id = 329,
113 .subtype = 13,
114 .range_start = 40,
115 .range_num = 3,
116 },
117 /* RX channels */
118 {
119 .dev_id = 329,
120 .subtype = 10,
121 .range_start = 40,
122 .range_num = 3,
123 },
124 /* RX Free flows */
125 {
126 .dev_id = 329,
127 .subtype = 0,
128 .range_start = 84,
129 .range_num = 8,
130 },
131 { },
132};
133#endif /* CONFIG_SOC_K3_J784S4 */
134
Vignesh Raghavendra4214a812021-06-07 19:47:48 +0530[diff] [blame]135#else
136static struct ti_sci_resource_static_data rm_static_data[] = {
137 { },
138};
139#endif /* CONFIG_K3_DM_FW */
140#endif /* __TI_SCI_STATIC_DATA_H */