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stroese75b80a02004-12-16 18:25:40 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
29/* ------------------------------------------------------------------------- */
30
31#if 0
32#define FPGA_DEBUG
33#endif
34
Wolfgang Denk6262d0212010-06-28 22:00:46 +020035extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
stroese75b80a02004-12-16 18:25:40 +000036
37/* fpga configuration data - gzip compressed and generated by bin2c */
38const unsigned char fpgadata[] =
39{
40#include "fpgadata.c"
41};
42
43/*
44 * include common fpga code (for esd boards)
45 */
46#include "../common/fpga.c"
47
48
stroese75b80a02004-12-16 18:25:40 +000049int board_early_init_f (void)
50{
51 /*
52 * IRQ 0-15 405GP internally generated; active high; level sensitive
53 * IRQ 16 405GP internally generated; active low; level sensitive
54 * IRQ 17-24 RESERVED
55 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
56 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
57 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
58 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
59 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
60 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
61 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
62 */
Stefan Roese707fd362009-09-24 09:55:50 +020063 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
64 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
65 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
66 mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
67 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
68 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
69 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
stroese75b80a02004-12-16 18:25:40 +000070
71 /*
72 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
73 */
Stefan Roese918010a2009-09-09 16:25:29 +020074 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
stroese75b80a02004-12-16 18:25:40 +000075
76 return 0;
77}
78
stroese75b80a02004-12-16 18:25:40 +000079int misc_init_r (void)
80{
stroese75b80a02004-12-16 18:25:40 +000081 unsigned char *dst;
82 ulong len = sizeof(fpgadata);
83 int status;
84 int index;
85 int i;
86
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
88 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
stroese75b80a02004-12-16 18:25:40 +000089 printf ("GUNZIP ERROR - must RESET board to recover\n");
90 do_reset (NULL, 0, 0, NULL);
91 }
92
93 status = fpga_boot(dst, len);
94 if (status != 0) {
95 printf("\nFPGA: Booting failed ");
96 switch (status) {
97 case ERROR_FPGA_PRG_INIT_LOW:
98 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
99 break;
100 case ERROR_FPGA_PRG_INIT_HIGH:
101 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
102 break;
103 case ERROR_FPGA_PRG_DONE:
104 printf("(Timeout: DONE not high after programming FPGA)\n ");
105 break;
106 }
107
108 /* display infos on fpgaimage */
109 index = 15;
110 for (i=0; i<4; i++) {
111 len = dst[index];
112 printf("FPGA: %s\n", &(dst[index+1]));
113 index += len+3;
114 }
115 putc ('\n');
116 /* delayed reboot */
117 for (i=20; i>0; i--) {
118 printf("Rebooting in %2d seconds \r",i);
119 for (index=0;index<1000;index++)
120 udelay(1000);
121 }
122 putc ('\n');
123 do_reset(NULL, 0, 0, NULL);
124 }
125
126 puts("FPGA: ");
127
128 /* display infos on fpgaimage */
129 index = 15;
130 for (i=0; i<4; i++) {
131 len = dst[index];
132 printf("%s ", &(dst[index+1]));
133 index += len+3;
134 }
135 putc ('\n');
136
137 free(dst);
138
139 /*
140 * Reset FPGA via FPGA_DATA pin
141 */
142 SET_FPGA(FPGA_PRG | FPGA_CLK);
143 udelay(1000); /* wait 1ms */
144 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
145 udelay(1000); /* wait 1ms */
146
147 /*
148 * Reset external DUARTs
149 */
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100150 out_be32((void *)GPIO0_OR,
151 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
stroese75b80a02004-12-16 18:25:40 +0000152 udelay(10); /* wait 10us */
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100153 out_be32((void *)GPIO0_OR,
154 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
stroese75b80a02004-12-16 18:25:40 +0000155 udelay(1000); /* wait 1ms */
156
157 /*
stroese75b80a02004-12-16 18:25:40 +0000158 * Enable interrupts in exar duart mcr[3]
159 */
Matthias Fuchsfaac7432009-02-20 10:19:18 +0100160 out_8((void *)(DUART0_BA + 4), 0x08);
161 out_8((void *)(DUART1_BA + 4), 0x08);
162 out_8((void *)(DUART2_BA + 4), 0x08);
163 out_8((void *)(DUART3_BA + 4), 0x08);
stroese75b80a02004-12-16 18:25:40 +0000164
165 return (0);
166}
167
168
169/*
170 * Check Board Identity:
171 */
172
173int checkboard (void)
174{
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200175 char str[64];
Wolfgang Denk76af2782010-07-24 21:55:43 +0200176 int i = getenv_f("serial#", str, sizeof(str));
stroese75b80a02004-12-16 18:25:40 +0000177
178 puts ("Board: ");
179
180 if (i == -1) {
181 puts ("### No HW ID - assuming WUH405");
182 } else {
183 puts(str);
184 }
185
186 putc ('\n');
187
188 return 0;
189}