blob: 67d215cbba8a48ddcab38f2ca9fd15c833cd11b1 [file] [log] [blame]
Jagan Tekid69bf0b2018-08-05 14:31:54 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050011#include <clk/sunxi.h>
Jagan Tekid69bf0b2018-08-05 14:31:54 +053012#include <dt-bindings/clock/sun8i-v3s-ccu.h>
13#include <dt-bindings/reset/sun8i-v3s-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Jagan Tekid69bf0b2018-08-05 14:31:54 +053015
16static struct ccu_clk_gate v3s_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +000017 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +053020 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053021 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22
Andre Przywara3e9aa0b2022-05-04 22:10:28 +010023 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
24
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050025 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
26 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +053027 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
28 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
29 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
30
Jagan Tekibc123132019-02-27 20:02:06 +053031 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
32
Jagan Tekid69bf0b2018-08-05 14:31:54 +053033 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
34};
35
36static struct ccu_reset v3s_resets[] = {
37 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
38
Andre Przywaraddf33c12019-01-29 15:54:09 +000039 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
40 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
41 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +053042 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053043 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
Jagan Tekib490aa52018-12-30 21:37:31 +053044
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050045 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
46 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
Jagan Tekib490aa52018-12-30 21:37:31 +053047 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
48 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
49 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053050};
51
52static const struct ccu_desc v3s_ccu_desc = {
53 .gates = v3s_gates,
54 .resets = v3s_resets,
55};
56
57static int v3s_clk_bind(struct udevice *dev)
58{
59 return sunxi_reset_bind(dev, ARRAY_SIZE(v3s_resets));
60}
61
62static const struct udevice_id v3s_clk_ids[] = {
63 { .compatible = "allwinner,sun8i-v3s-ccu",
64 .data = (ulong)&v3s_ccu_desc },
Icenowy Zheng18e4ab62020-10-26 22:18:02 +080065 { .compatible = "allwinner,sun8i-v3-ccu",
66 .data = (ulong)&v3s_ccu_desc },
Jagan Tekid69bf0b2018-08-05 14:31:54 +053067 { }
68};
69
70U_BOOT_DRIVER(clk_sun8i_v3s) = {
71 .name = "sun8i_v3s_ccu",
72 .id = UCLASS_CLK,
73 .of_match = v3s_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -070074 .priv_auto = sizeof(struct ccu_priv),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053075 .ops = &sunxi_clk_ops,
76 .probe = sunxi_clk_probe,
77 .bind = v3s_clk_bind,
78};