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git01.mediatek.com / filogic / uboot / 18bbf96e1b6136d6fe8fd33c86707694f3f1c5de / . / drivers / pinctrl / meson / pinctrl-meson-gxbb.c
blob: 87c9912c02a9b97b4e462550cc801fef7e5d2641 [file] [log] [blame]
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]1/*
2 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
3 *
4 * Based on code from Linux kernel:
5 * Copyright (C) 2016 Endless Mobile, Inc.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
Simon Glass51a3ec32017-05-17 17:18:07 -0600[diff] [blame]10#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -0600[diff] [blame]11#include <dm.h>
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]12#include <dm/pinctrl.h>
13#include <dt-bindings/gpio/meson-gxbb-gpio.h>
14
15#include "pinctrl-meson.h"
16
17#define EE_OFF 14
18
19static const unsigned int emmc_nand_d07_pins[] = {
20 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
21 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
22 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
23};
24static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
25static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
26static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
27
28static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
29static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
30static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
31static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
32static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
33static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
34
35static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
36static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
37static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) };
38static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) };
39
40static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) };
41static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) };
42static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
43static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
44
45static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_13, EE_OFF) };
46static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) };
47static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) };
48static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) };
49
50static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
51static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
52static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
53static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
54static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
55static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
56static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
57static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
58static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
59static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) };
60static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
61static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
62static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
63static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
64
65static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
66static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
67static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
68static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
69static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
70static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
71 PIN(GPIOAO_5, 0) };
72static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
73static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
74
75static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
76static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
77static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
78static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
79
80static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
81 GPIO_GROUP(GPIOZ_0, EE_OFF),
82 GPIO_GROUP(GPIOZ_1, EE_OFF),
83 GPIO_GROUP(GPIOZ_2, EE_OFF),
84 GPIO_GROUP(GPIOZ_3, EE_OFF),
85 GPIO_GROUP(GPIOZ_4, EE_OFF),
86 GPIO_GROUP(GPIOZ_5, EE_OFF),
87 GPIO_GROUP(GPIOZ_6, EE_OFF),
88 GPIO_GROUP(GPIOZ_7, EE_OFF),
89 GPIO_GROUP(GPIOZ_8, EE_OFF),
90 GPIO_GROUP(GPIOZ_9, EE_OFF),
91 GPIO_GROUP(GPIOZ_10, EE_OFF),
92 GPIO_GROUP(GPIOZ_11, EE_OFF),
93 GPIO_GROUP(GPIOZ_12, EE_OFF),
94 GPIO_GROUP(GPIOZ_13, EE_OFF),
95 GPIO_GROUP(GPIOZ_14, EE_OFF),
96 GPIO_GROUP(GPIOZ_15, EE_OFF),
97
98 GPIO_GROUP(GPIOH_0, EE_OFF),
99 GPIO_GROUP(GPIOH_1, EE_OFF),
100 GPIO_GROUP(GPIOH_2, EE_OFF),
101 GPIO_GROUP(GPIOH_3, EE_OFF),
102
103 GPIO_GROUP(BOOT_0, EE_OFF),
104 GPIO_GROUP(BOOT_1, EE_OFF),
105 GPIO_GROUP(BOOT_2, EE_OFF),
106 GPIO_GROUP(BOOT_3, EE_OFF),
107 GPIO_GROUP(BOOT_4, EE_OFF),
108 GPIO_GROUP(BOOT_5, EE_OFF),
109 GPIO_GROUP(BOOT_6, EE_OFF),
110 GPIO_GROUP(BOOT_7, EE_OFF),
111 GPIO_GROUP(BOOT_8, EE_OFF),
112 GPIO_GROUP(BOOT_9, EE_OFF),
113 GPIO_GROUP(BOOT_10, EE_OFF),
114 GPIO_GROUP(BOOT_11, EE_OFF),
115 GPIO_GROUP(BOOT_12, EE_OFF),
116 GPIO_GROUP(BOOT_13, EE_OFF),
117 GPIO_GROUP(BOOT_14, EE_OFF),
118 GPIO_GROUP(BOOT_15, EE_OFF),
119 GPIO_GROUP(BOOT_16, EE_OFF),
120 GPIO_GROUP(BOOT_17, EE_OFF),
121
122 GPIO_GROUP(CARD_0, EE_OFF),
123 GPIO_GROUP(CARD_1, EE_OFF),
124 GPIO_GROUP(CARD_2, EE_OFF),
125 GPIO_GROUP(CARD_3, EE_OFF),
126 GPIO_GROUP(CARD_4, EE_OFF),
127 GPIO_GROUP(CARD_5, EE_OFF),
128 GPIO_GROUP(CARD_6, EE_OFF),
129
130 GPIO_GROUP(GPIODV_0, EE_OFF),
131 GPIO_GROUP(GPIODV_1, EE_OFF),
132 GPIO_GROUP(GPIODV_2, EE_OFF),
133 GPIO_GROUP(GPIODV_3, EE_OFF),
134 GPIO_GROUP(GPIODV_4, EE_OFF),
135 GPIO_GROUP(GPIODV_5, EE_OFF),
136 GPIO_GROUP(GPIODV_6, EE_OFF),
137 GPIO_GROUP(GPIODV_7, EE_OFF),
138 GPIO_GROUP(GPIODV_8, EE_OFF),
139 GPIO_GROUP(GPIODV_9, EE_OFF),
140 GPIO_GROUP(GPIODV_10, EE_OFF),
141 GPIO_GROUP(GPIODV_11, EE_OFF),
142 GPIO_GROUP(GPIODV_12, EE_OFF),
143 GPIO_GROUP(GPIODV_13, EE_OFF),
144 GPIO_GROUP(GPIODV_14, EE_OFF),
145 GPIO_GROUP(GPIODV_15, EE_OFF),
146 GPIO_GROUP(GPIODV_16, EE_OFF),
147 GPIO_GROUP(GPIODV_17, EE_OFF),
148 GPIO_GROUP(GPIODV_19, EE_OFF),
149 GPIO_GROUP(GPIODV_20, EE_OFF),
150 GPIO_GROUP(GPIODV_21, EE_OFF),
151 GPIO_GROUP(GPIODV_22, EE_OFF),
152 GPIO_GROUP(GPIODV_23, EE_OFF),
153 GPIO_GROUP(GPIODV_24, EE_OFF),
154 GPIO_GROUP(GPIODV_25, EE_OFF),
155 GPIO_GROUP(GPIODV_26, EE_OFF),
156 GPIO_GROUP(GPIODV_27, EE_OFF),
157 GPIO_GROUP(GPIODV_28, EE_OFF),
158 GPIO_GROUP(GPIODV_29, EE_OFF),
159
160 GPIO_GROUP(GPIOY_0, EE_OFF),
161 GPIO_GROUP(GPIOY_1, EE_OFF),
162 GPIO_GROUP(GPIOY_2, EE_OFF),
163 GPIO_GROUP(GPIOY_3, EE_OFF),
164 GPIO_GROUP(GPIOY_4, EE_OFF),
165 GPIO_GROUP(GPIOY_5, EE_OFF),
166 GPIO_GROUP(GPIOY_6, EE_OFF),
167 GPIO_GROUP(GPIOY_7, EE_OFF),
168 GPIO_GROUP(GPIOY_8, EE_OFF),
169 GPIO_GROUP(GPIOY_9, EE_OFF),
170 GPIO_GROUP(GPIOY_10, EE_OFF),
171 GPIO_GROUP(GPIOY_11, EE_OFF),
172 GPIO_GROUP(GPIOY_12, EE_OFF),
173 GPIO_GROUP(GPIOY_13, EE_OFF),
174 GPIO_GROUP(GPIOY_14, EE_OFF),
175 GPIO_GROUP(GPIOY_15, EE_OFF),
176 GPIO_GROUP(GPIOY_16, EE_OFF),
177
178 GPIO_GROUP(GPIOX_0, EE_OFF),
179 GPIO_GROUP(GPIOX_1, EE_OFF),
180 GPIO_GROUP(GPIOX_2, EE_OFF),
181 GPIO_GROUP(GPIOX_3, EE_OFF),
182 GPIO_GROUP(GPIOX_4, EE_OFF),
183 GPIO_GROUP(GPIOX_5, EE_OFF),
184 GPIO_GROUP(GPIOX_6, EE_OFF),
185 GPIO_GROUP(GPIOX_7, EE_OFF),
186 GPIO_GROUP(GPIOX_8, EE_OFF),
187 GPIO_GROUP(GPIOX_9, EE_OFF),
188 GPIO_GROUP(GPIOX_10, EE_OFF),
189 GPIO_GROUP(GPIOX_11, EE_OFF),
190 GPIO_GROUP(GPIOX_12, EE_OFF),
191 GPIO_GROUP(GPIOX_13, EE_OFF),
192 GPIO_GROUP(GPIOX_14, EE_OFF),
193 GPIO_GROUP(GPIOX_15, EE_OFF),
194 GPIO_GROUP(GPIOX_16, EE_OFF),
195 GPIO_GROUP(GPIOX_17, EE_OFF),
196 GPIO_GROUP(GPIOX_18, EE_OFF),
197 GPIO_GROUP(GPIOX_19, EE_OFF),
198 GPIO_GROUP(GPIOX_20, EE_OFF),
199 GPIO_GROUP(GPIOX_21, EE_OFF),
200 GPIO_GROUP(GPIOX_22, EE_OFF),
201
202 GPIO_GROUP(GPIOCLK_0, EE_OFF),
203 GPIO_GROUP(GPIOCLK_1, EE_OFF),
204 GPIO_GROUP(GPIOCLK_2, EE_OFF),
205 GPIO_GROUP(GPIOCLK_3, EE_OFF),
206
207 GPIO_GROUP(GPIO_TEST_N, EE_OFF),
208
209 /* Bank X */
210 GROUP(uart_tx_a, 4, 13),
211 GROUP(uart_rx_a, 4, 12),
212 GROUP(uart_cts_a, 4, 11),
213 GROUP(uart_rts_a, 4, 10),
214
215 /* Bank Y */
216 GROUP(uart_cts_c, 1, 19),
217 GROUP(uart_rts_c, 1, 18),
218 GROUP(uart_tx_c, 1, 17),
219 GROUP(uart_rx_c, 1, 16),
220
221 /* Bank Z */
222 GROUP(eth_mdio, 6, 1),
223 GROUP(eth_mdc, 6, 0),
224 GROUP(eth_clk_rx_clk, 6, 13),
225 GROUP(eth_rx_dv, 6, 12),
226 GROUP(eth_rxd0, 6, 11),
227 GROUP(eth_rxd1, 6, 10),
228 GROUP(eth_rxd2, 6, 9),
229 GROUP(eth_rxd3, 6, 8),
230 GROUP(eth_rgmii_tx_clk, 6, 7),
231 GROUP(eth_tx_en, 6, 6),
232 GROUP(eth_txd0, 6, 5),
233 GROUP(eth_txd1, 6, 4),
234 GROUP(eth_txd2, 6, 3),
235 GROUP(eth_txd3, 6, 2),
236
237 /* Bank DV */
238 GROUP(uart_tx_b, 2, 29),
239 GROUP(uart_rx_b, 2, 28),
240 GROUP(uart_cts_b, 2, 27),
241 GROUP(uart_rts_b, 2, 26),
242
243 /* Bank BOOT */
244 GROUP(emmc_nand_d07, 4, 30),
245 GROUP(emmc_clk, 4, 18),
246 GROUP(emmc_cmd, 4, 19),
247 GROUP(emmc_ds, 4, 31),
248
249 /* Bank CARD */
250 GROUP(sdcard_d1, 2, 14),
251 GROUP(sdcard_d0, 2, 15),
252 GROUP(sdcard_d3, 2, 12),
253 GROUP(sdcard_d2, 2, 13),
254 GROUP(sdcard_cmd, 2, 10),
255 GROUP(sdcard_clk, 2, 11),
256};
257
258static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
259 GPIO_GROUP(GPIOAO_0, 0),
260 GPIO_GROUP(GPIOAO_1, 0),
261 GPIO_GROUP(GPIOAO_2, 0),
262 GPIO_GROUP(GPIOAO_3, 0),
263 GPIO_GROUP(GPIOAO_4, 0),
264 GPIO_GROUP(GPIOAO_5, 0),
265 GPIO_GROUP(GPIOAO_6, 0),
266 GPIO_GROUP(GPIOAO_7, 0),
267 GPIO_GROUP(GPIOAO_8, 0),
268 GPIO_GROUP(GPIOAO_9, 0),
269 GPIO_GROUP(GPIOAO_10, 0),
270 GPIO_GROUP(GPIOAO_11, 0),
271 GPIO_GROUP(GPIOAO_12, 0),
272 GPIO_GROUP(GPIOAO_13, 0),
273
274 /* bank AO */
275 GROUP(uart_tx_ao_b, 0, 26),
276 GROUP(uart_rx_ao_b, 0, 25),
277 GROUP(uart_tx_ao_a, 0, 12),
278 GROUP(uart_rx_ao_a, 0, 11),
279 GROUP(uart_cts_ao_a, 0, 10),
280 GROUP(uart_rts_ao_a, 0, 9),
281 GROUP(uart_cts_ao_b, 0, 8),
282 GROUP(uart_rts_ao_b, 0, 7),
283 GROUP(i2c_sck_ao, 0, 6),
284 GROUP(i2c_sda_ao, 0, 5),
285 GROUP(i2c_slave_sck_ao, 0, 2),
286 GROUP(i2c_slave_sda_ao, 0, 1),
287};
288
289static const char * const gpio_periphs_groups[] = {
290 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
291 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
292 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
293 "GPIOZ_15",
294
295 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3",
296
297 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
298 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
299 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
300 "BOOT_15", "BOOT_16", "BOOT_17",
301
302 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
303 "CARD_5", "CARD_6",
304
305 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
306 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
307 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
308 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
309 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
310 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
311
312 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
313 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
314 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
315 "GPIOY_15", "GPIOY_16",
316
317 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
318 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
319 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
320 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
321 "GPIOX_20", "GPIOX_21", "GPIOX_22",
322
323 "GPIO_TEST_N",
324};
325
326static const char * const emmc_groups[] = {
327 "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
328};
329
330static const char * const sdcard_groups[] = {
331 "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
332 "sdcard_cmd", "sdcard_clk",
333};
334
335static const char * const uart_a_groups[] = {
336 "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
337};
338
339static const char * const uart_b_groups[] = {
340 "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
341};
342
343static const char * const uart_c_groups[] = {
344 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
345};
346
347static const char * const eth_groups[] = {
348 "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
349 "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
350 "eth_rgmii_tx_clk", "eth_tx_en",
351 "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
352};
353
354static const char * const gpio_aobus_groups[] = {
355 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
356 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
357 "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
358};
359
360static const char * const uart_ao_groups[] = {
361 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
362};
363
364static const char * const uart_ao_b_groups[] = {
365 "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
366};
367
368static const char * const i2c_ao_groups[] = {
369 "i2c_sdk_ao", "i2c_sda_ao",
370};
371
372static const char * const i2c_slave_ao_groups[] = {
373 "i2c_slave_sdk_ao", "i2c_slave_sda_ao",
374};
375
376static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
377 FUNCTION(gpio_periphs),
378 FUNCTION(emmc),
379 FUNCTION(sdcard),
380 FUNCTION(uart_a),
381 FUNCTION(uart_b),
382 FUNCTION(uart_c),
383 FUNCTION(eth),
384};
385
386static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
387 FUNCTION(gpio_aobus),
388 FUNCTION(uart_ao),
389 FUNCTION(uart_ao_b),
390 FUNCTION(i2c_ao),
391 FUNCTION(i2c_slave_ao),
392};
393
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200[diff] [blame]394static struct meson_bank meson_gxbb_periphs_banks[] = {
395 /* name first last pullen pull dir out in */
396 BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
397 BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
398 BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
399 BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
400 BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
401 BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
402 BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
403 BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
404};
405
406static struct meson_bank meson_gxbb_aobus_banks[] = {
407 /* name first last pullen pull dir out in */
408 BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
409};
410
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]411struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
412 .name = "periphs-banks",
413 .pin_base = 14,
414 .groups = meson_gxbb_periphs_groups,
415 .funcs = meson_gxbb_periphs_functions,
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200[diff] [blame]416 .banks = meson_gxbb_periphs_banks,
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]417 .num_pins = 120,
418 .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
419 .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200[diff] [blame]420 .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]421};
422
423struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
424 .name = "aobus-banks",
425 .pin_base = 0,
426 .groups = meson_gxbb_aobus_groups,
427 .funcs = meson_gxbb_aobus_functions,
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200[diff] [blame]428 .banks = meson_gxbb_aobus_banks,
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]429 .num_pins = 14,
430 .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
431 .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200[diff] [blame]432 .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]433};
434
435static const struct udevice_id meson_gxbb_pinctrl_match[] = {
436 {
437 .compatible = "amlogic,meson-gxbb-periphs-pinctrl",
438 .data = (ulong)&meson_gxbb_periphs_pinctrl_data,
439 },
440 {
441 .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
442 .data = (ulong)&meson_gxbb_aobus_pinctrl_data,
443 },
444 { /* sentinel */ }
445};
446
447U_BOOT_DRIVER(meson_gxbb_pinctrl) = {
448 .name = "meson-gxbb-pinctrl",
449 .id = UCLASS_PINCTRL,
450 .of_match = of_match_ptr(meson_gxbb_pinctrl_match),
451 .probe = meson_pinctrl_probe,
452 .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
453 .ops = &meson_pinctrl_ops,
454};