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git01.mediatek.com / filogic / uboot / 186e64ec030c1ded14f1b2df07bcc59e38114391 / . / board / prodrive / alpr / init.S
blob: 7ff7a59170e1b5828b38af57336c809ba5e3c877 [file] [log] [blame]
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]1/*
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]6 */
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]7
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]8#include <asm-offsets.h>
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]9#include <ppc_asm.tmpl>
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]10#include <asm/mmu.h>
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]11#include <config.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]12#include <asm/ppc4xx.h>
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]13
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]14/**************************************************************************
15 * TLB TABLE
16 *
17 * This table is used by the cpu boot code to setup the initial tlb
18 * entries. Rather than make broad assumptions in the cpu source tree,
19 * this table lets each board set things up however they like.
20 *
21 * Pointer to the table is returned in r1
22 *
23 *************************************************************************/
24
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]25 .section .bootpg,"ax"
26 .globl tlbtab
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]27
28tlbtab:
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]29 tlbtab_start
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]30 tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
31 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
32 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
33 tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]34#ifdef CONFIG_4xx_DCACHE
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]35 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]36#else
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]37 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]38#endif
39
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]40#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]41 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]42 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
Pieter Voorthuijsenbeef5172008-03-17 09:27:56 +0100[diff] [blame]43#endif
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]44 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]45
46 /* PCI */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]47 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
48 tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
49 tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
Stefan Roese49639682006-08-15 14:22:35 +0200[diff] [blame]50
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]51 /* NAND */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]52 tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
Stefan Roesea1831882006-10-07 11:35:25 +0200[diff] [blame]53 tlbtab_end