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git01.mediatek.com / filogic / uboot / 18668a4d53f85916cfa945a71e72fe8fa50a49d0 / . / arch / arm / dts / k3-am654-base-board-u-boot.dtsi
blob: 143eb6d63092bb9c7e1f2a3dde85b0d165abe543 [file] [log] [blame]
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6#include <dt-bindings/pinctrl/k3-am65.h>
7
8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 };
12
13 aliases {
14 serial2 = &main_uart0;
15 };
16};
17
18&cbass_main{
19 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]20
21 main_pmx0: pinmux@11c000 {
22 compatible = "pinctrl-single";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]23 reg = <0x0 0x11c000 0x0 0x2e4>;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]24 #pinctrl-cells = <1>;
25 pinctrl-single,register-width = <32>;
26 pinctrl-single,function-mask = <0xffffffff>;
27 };
28
29 main_pmx1: pinmux@11c2e8 {
30 compatible = "pinctrl-single";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]31 reg = <0x0 0x11c2e8 0x0 0x24>;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]32 #pinctrl-cells = <1>;
33 pinctrl-single,register-width = <32>;
34 pinctrl-single,function-mask = <0xffffffff>;
35 };
36
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]37 sdhci0: sdhci@04F80000 {
38 compatible = "arasan,sdhci-5.1";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]39 reg = <0x0 0x4F80000 0x0 0x1000>,
40 <0x0 0x4F90000 0x0 0x400>;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]41 clocks = <&k3_clks 47 1>;
42 power-domains = <&k3_pds 47>;
43 max-frequency = <25000000>;
44 };
45
46 sdhci1: sdhci@04FA0000 {
47 compatible = "arasan,sdhci-5.1";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]48 reg = <0x0 0x4FA0000 0x0 0x1000>,
49 <0x0 0x4FB0000 0x0 0x400>;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]50 clocks = <&k3_clks 48 1>;
51 power-domains = <&k3_pds 48>;
52 max-frequency = <25000000>;
53 };
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]54
55};
56
57&cbass_mcu {
58 u-boot,dm-spl;
59 wkup_pmx0: pinmux@4301c000 {
60 compatible = "pinctrl-single";
61 reg = <0x0 0x4301c000 0x0 0x118>;
62 #pinctrl-cells = <1>;
63 pinctrl-single,register-width = <32>;
64 pinctrl-single,function-mask = <0xffffffff>;
65 };
66};
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]67
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]68&cbass_wakeup {
69 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]70};
71
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]72&secure_proxy_main {
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]73 u-boot,dm-spl;
74};
75
76&dmsc {
77 u-boot,dm-spl;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]78 k3_sysreset: sysreset-controller {
79 compatible = "ti,sci-sysreset";
80 u-boot,dm-spl;
81 };
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]82};
83
84&k3_pds {
85 u-boot,dm-spl;
86};
87
88&k3_clks {
89 u-boot,dm-spl;
90};
91
92&k3_reset {
93 u-boot,dm-spl;
94};
95
96&main_pmx0 {
97 u-boot,dm-spl;
98 main_uart0_pins_default: main_uart0_pins_default {
99 pinctrl-single,pins = <
100 AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */
101 AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */
102 AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */
103 AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */
104 >;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]105 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]106 };
107
108 main_mmc0_pins_default: main_mmc0_pins_default {
109 pinctrl-single,pins = <
110 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */
111 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */
112 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */
113 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */
114 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */
115 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */
116 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */
117 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */
118 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */
119 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */
120 AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */
121 >;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]122 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]123 };
124
125 main_mmc1_pins_default: main_mmc1_pins_default {
126 pinctrl-single,pins = <
127 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */
128 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */
129 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */
130 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */
131 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */
132 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */
133 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */
134 AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */
135 >;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]136 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]137 };
138
139};
140
141&main_pmx1 {
142 u-boot,dm-spl;
143};
144
145&main_uart0 {
146 u-boot,dm-spl;
147 pinctrl-names = "default";
148 pinctrl-0 = <&main_uart0_pins_default>;
149 status = "okay";
150};
151
152&sdhci0 {
153 u-boot,dm-spl;
154 status = "okay";
155 non-removable;
156 bus-width = <8>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&main_mmc0_pins_default>;
159};
160
161&sdhci1 {
162 u-boot,dm-spl;
163 status = "okay";
164 pinctrl-names = "default";
165 pinctrl-0 = <&main_mmc1_pins_default>;
166 sdhci-caps-mask = <0x7 0x0>;
167};