Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 OpenMoko, Inc. |
| 3 | * Author: Harald Welte <laforge@openmoko.org> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 10 | #include <nand.h> |
kevin.morfitt@fearnside-systems.co.uk | e0d8131 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 11 | #include <asm/arch/s3c24x0_cpu.h> |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 12 | #include <asm/io.h> |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 13 | |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 14 | #define S3C2410_NFCONF_EN (1<<15) |
| 15 | #define S3C2410_NFCONF_512BYTE (1<<14) |
| 16 | #define S3C2410_NFCONF_4STEP (1<<13) |
| 17 | #define S3C2410_NFCONF_INITECC (1<<12) |
| 18 | #define S3C2410_NFCONF_nFCE (1<<11) |
| 19 | #define S3C2410_NFCONF_TACLS(x) ((x)<<8) |
| 20 | #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) |
| 21 | #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) |
| 22 | |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 23 | #define S3C2410_ADDR_NALE 4 |
| 24 | #define S3C2410_ADDR_NCLE 8 |
| 25 | |
Hui.Tang | a5176e0 | 2009-11-18 16:24:04 +0800 | [diff] [blame] | 26 | #ifdef CONFIG_NAND_SPL |
| 27 | |
| 28 | /* in the early stage of NAND flash booting, printf() is not available */ |
| 29 | #define printf(fmt, args...) |
| 30 | |
| 31 | static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 32 | { |
| 33 | int i; |
Scott Wood | 17fed14 | 2016-05-30 13:57:56 -0500 | [diff] [blame^] | 34 | struct nand_chip *this = mtd_to_nand(mtd); |
Hui.Tang | a5176e0 | 2009-11-18 16:24:04 +0800 | [diff] [blame] | 35 | |
| 36 | for (i = 0; i < len; i++) |
| 37 | buf[i] = readb(this->IO_ADDR_R); |
| 38 | } |
| 39 | #endif |
| 40 | |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 41 | static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 42 | { |
Scott Wood | 17fed14 | 2016-05-30 13:57:56 -0500 | [diff] [blame^] | 43 | struct nand_chip *chip = mtd_to_nand(mtd); |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 44 | struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 45 | |
Marek Vasut | 04a7a4e | 2011-10-24 23:40:04 +0000 | [diff] [blame] | 46 | debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 47 | |
| 48 | if (ctrl & NAND_CTRL_CHANGE) { |
kevin.morfitt@fearnside-systems.co.uk | 0d17ec5 | 2009-10-10 13:34:09 +0900 | [diff] [blame] | 49 | ulong IO_ADDR_W = (ulong)nand; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 50 | |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 51 | if (!(ctrl & NAND_CLE)) |
| 52 | IO_ADDR_W |= S3C2410_ADDR_NCLE; |
| 53 | if (!(ctrl & NAND_ALE)) |
| 54 | IO_ADDR_W |= S3C2410_ADDR_NALE; |
| 55 | |
| 56 | chip->IO_ADDR_W = (void *)IO_ADDR_W; |
| 57 | |
| 58 | if (ctrl & NAND_NCE) |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 59 | writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, |
| 60 | &nand->nfconf); |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 61 | else |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 62 | writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, |
| 63 | &nand->nfconf); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 64 | } |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 65 | |
| 66 | if (cmd != NAND_CMD_NONE) |
| 67 | writeb(cmd, chip->IO_ADDR_W); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 68 | } |
| 69 | |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 70 | static int s3c24x0_dev_ready(struct mtd_info *mtd) |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 71 | { |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 72 | struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); |
Marek Vasut | 04a7a4e | 2011-10-24 23:40:04 +0000 | [diff] [blame] | 73 | debug("dev_ready\n"); |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 74 | return readl(&nand->nfstat) & 0x01; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | #ifdef CONFIG_S3C2410_NAND_HWECC |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 78 | void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 79 | { |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 80 | struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); |
| 81 | debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode); |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 82 | writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 83 | } |
| 84 | |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 85 | static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 86 | u_char *ecc_code) |
| 87 | { |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 88 | struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 89 | ecc_code[0] = readb(&nand->nfecc); |
| 90 | ecc_code[1] = readb(&nand->nfecc + 1); |
| 91 | ecc_code[2] = readb(&nand->nfecc + 2); |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 92 | debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", |
| 93 | mtd , ecc_code[0], ecc_code[1], ecc_code[2]); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 98 | static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 99 | u_char *read_ecc, u_char *calc_ecc) |
| 100 | { |
| 101 | if (read_ecc[0] == calc_ecc[0] && |
| 102 | read_ecc[1] == calc_ecc[1] && |
| 103 | read_ecc[2] == calc_ecc[2]) |
| 104 | return 0; |
| 105 | |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 106 | printf("s3c24x0_nand_correct_data: not implemented\n"); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 107 | return -1; |
| 108 | } |
| 109 | #endif |
| 110 | |
| 111 | int board_nand_init(struct nand_chip *nand) |
| 112 | { |
| 113 | u_int32_t cfg; |
| 114 | u_int8_t tacls, twrph0, twrph1; |
kevin.morfitt@fearnside-systems.co.uk | 0d17ec5 | 2009-10-10 13:34:09 +0900 | [diff] [blame] | 115 | struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 116 | struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand(); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 117 | |
Marek Vasut | 04a7a4e | 2011-10-24 23:40:04 +0000 | [diff] [blame] | 118 | debug("board_nand_init()\n"); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 119 | |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 120 | writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 121 | |
| 122 | /* initialize hardware */ |
David Müller (ELSOFT AG) | e03effe | 2010-11-29 05:49:19 +0000 | [diff] [blame] | 123 | #if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING) |
| 124 | tacls = CONFIG_S3C24XX_TACLS; |
| 125 | twrph0 = CONFIG_S3C24XX_TWRPH0; |
| 126 | twrph1 = CONFIG_S3C24XX_TWRPH1; |
| 127 | #else |
| 128 | tacls = 4; |
| 129 | twrph0 = 8; |
| 130 | twrph1 = 8; |
| 131 | #endif |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 132 | |
| 133 | cfg = S3C2410_NFCONF_EN; |
| 134 | cfg |= S3C2410_NFCONF_TACLS(tacls - 1); |
| 135 | cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); |
| 136 | cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 137 | writel(cfg, &nand_reg->nfconf); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 138 | |
| 139 | /* initialize nand_chip data structure */ |
C Nauman | 383c43e | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 140 | nand->IO_ADDR_R = (void *)&nand_reg->nfdata; |
| 141 | nand->IO_ADDR_W = (void *)&nand_reg->nfdata; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 142 | |
Hui.Tang | a5176e0 | 2009-11-18 16:24:04 +0800 | [diff] [blame] | 143 | nand->select_chip = NULL; |
| 144 | |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 145 | /* read_buf and write_buf are default */ |
| 146 | /* read_byte and write_byte are default */ |
Hui.Tang | a5176e0 | 2009-11-18 16:24:04 +0800 | [diff] [blame] | 147 | #ifdef CONFIG_NAND_SPL |
| 148 | nand->read_buf = nand_read_buf; |
| 149 | #endif |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 150 | |
| 151 | /* hwcontrol always must be implemented */ |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 152 | nand->cmd_ctrl = s3c24x0_hwcontrol; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 153 | |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 154 | nand->dev_ready = s3c24x0_dev_ready; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 155 | |
| 156 | #ifdef CONFIG_S3C2410_NAND_HWECC |
Marek Vasut | 9bfc6cc | 2014-10-11 18:42:52 +0200 | [diff] [blame] | 157 | nand->ecc.hwctl = s3c24x0_nand_enable_hwecc; |
| 158 | nand->ecc.calculate = s3c24x0_nand_calculate_ecc; |
| 159 | nand->ecc.correct = s3c24x0_nand_correct_data; |
Hui.Tang | a5176e0 | 2009-11-18 16:24:04 +0800 | [diff] [blame] | 160 | nand->ecc.mode = NAND_ECC_HW; |
| 161 | nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; |
| 162 | nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; |
Sergey Lapin | 3a38a55 | 2013-01-14 03:46:50 +0000 | [diff] [blame] | 163 | nand->ecc.strength = 1; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 164 | #else |
Scott Wood | 03f6ec3 | 2008-08-13 17:04:30 -0500 | [diff] [blame] | 165 | nand->ecc.mode = NAND_ECC_SOFT; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 166 | #endif |
| 167 | |
| 168 | #ifdef CONFIG_S3C2410_NAND_BBT |
Daniel Schwierzeck | f9f6c1f | 2013-06-08 23:00:15 +0200 | [diff] [blame] | 169 | nand->bbt_options |= NAND_BBT_USE_FLASH; |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 170 | #endif |
| 171 | |
Marek Vasut | 04a7a4e | 2011-10-24 23:40:04 +0000 | [diff] [blame] | 172 | debug("end of nand_init\n"); |
Harald Welte | 06a4fc0 | 2007-12-19 15:10:52 +0100 | [diff] [blame] | 173 | |
| 174 | return 0; |
| 175 | } |