Dirk Eibach | 43fed3c | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 4 | * |
| 5 | * Based on include/configs/yosemite.h |
| 6 | * (C) Copyright 2005-2007 |
| 7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module |
| 30 | */ |
| 31 | #ifndef __CONFIG_H |
| 32 | #define __CONFIG_H |
| 33 | |
| 34 | /* |
| 35 | * High Level Configuration Options |
| 36 | */ |
| 37 | #define CONFIG_440GR 1 /* Specific PPC440GR support */ |
| 38 | #define CONFIG_HOSTNAME gdppc440etx |
| 39 | #define CONFIG_440 1 /* ... PPC440 family */ |
| 40 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| 41 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
| 42 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| 44 | |
Dirk Eibach | 43fed3c | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 45 | /* |
| 46 | * Include common defines/options for all AMCC eval boards |
| 47 | */ |
| 48 | #include "amcc-common.h" |
| 49 | |
| 50 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ |
| 51 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
| 52 | |
| 53 | /* |
| 54 | * Base addresses -- Note these are effective addresses where the |
| 55 | * actual resources get mapped (not physical addresses) |
| 56 | */ |
| 57 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
| 58 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ |
| 59 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 |
| 60 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 |
| 61 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 |
| 62 | |
| 63 | /*Don't change either of these*/ |
Dirk Eibach | 43fed3c | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 64 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ |
| 65 | /*Don't change either of these*/ |
| 66 | |
| 67 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
| 68 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
| 69 | |
| 70 | /* |
| 71 | * Initial RAM & stack pointer (placed in SDRAM) |
| 72 | */ |
| 73 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ |
| 74 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 77 | - GENERATED_GBL_DATA_SIZE) |
Dirk Eibach | 43fed3c | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 78 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 79 | |
| 80 | /* |
| 81 | * Serial Port |
| 82 | */ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 83 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
| 84 | #define CONFIG_SYS_NS16550 |
| 85 | #define CONFIG_SYS_NS16550_SERIAL |
| 86 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 87 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Dirk Eibach | 43fed3c | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 88 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
Dirk Eibach | 43fed3c | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * Environment |
| 92 | * Define here the location of the environment variables (FLASH or EEPROM). |
| 93 | * Note: DENX encourages to use redundant environment in FLASH. |
| 94 | */ |
| 95 | #define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ |
| 96 | |
| 97 | /* |
| 98 | * FLASH related |
| 99 | */ |
| 100 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ |
| 101 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 102 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ |
| 103 | |
| 104 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 105 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ |
| 106 | |
| 107 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ |
| 108 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ |
| 109 | |
| 110 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ |
| 111 | |
| 112 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 113 | |
| 114 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 115 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ |
| 116 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
| 117 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ |
| 118 | |
| 119 | /* Address and size of Redundant Environment Sector */ |
| 120 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 121 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| 122 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
| 123 | |
| 124 | /* |
| 125 | * DDR SDRAM |
| 126 | */ |
| 127 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ |
| 128 | #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
| 129 | #define CONFIG_SYS_SDRAM_BANKS (2) |
| 130 | |
| 131 | #define CONFIG_SDRAM_BANK0 |
| 132 | #define CONFIG_SDRAM_BANK1 |
| 133 | |
| 134 | #define CONFIG_SYS_SDRAM0_TR0 0x410a4012 |
| 135 | #define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 |
| 136 | #define CONFIG_SYS_SDRAM0_RTR 0x04080000 |
| 137 | #define CONFIG_SYS_SDRAM0_CFG0 0x80000000 |
| 138 | |
| 139 | #undef CONFIG_SDRAM_ECC |
| 140 | |
| 141 | /* |
| 142 | * I2C |
| 143 | */ |
| 144 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ |
| 145 | |
| 146 | /* |
| 147 | * Default environment variables |
| 148 | */ |
| 149 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 150 | CONFIG_AMCC_DEF_ENV \ |
| 151 | CONFIG_AMCC_DEF_ENV_POWERPC \ |
| 152 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
| 153 | "kernel_addr=fc000000\0" \ |
| 154 | "ramdisk_addr=fc180000\0" \ |
| 155 | "" |
| 156 | |
| 157 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 158 | #define CONFIG_PHY_ADDR 1 |
| 159 | #define CONFIG_PHY1_ADDR 3 |
| 160 | |
| 161 | #ifdef DEBUG |
| 162 | #define CONFIG_PANIC_HANG |
| 163 | #endif |
| 164 | |
| 165 | /* |
| 166 | * Commands additional to the ones defined in amcc-common.h |
| 167 | */ |
| 168 | #define CONFIG_CMD_PCI |
| 169 | #undef CONFIG_CMD_EEPROM |
| 170 | |
| 171 | /* |
| 172 | * PCI stuff |
| 173 | */ |
| 174 | |
| 175 | /* General PCI */ |
| 176 | #define CONFIG_PCI /* include pci support */ |
| 177 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
| 178 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ |
| 179 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ |
| 180 | CONFIG_SYS_PCI_MEMBASE*/ |
| 181 | |
| 182 | /* Board-specific PCI */ |
| 183 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 184 | #define CONFIG_SYS_PCI_MASTER_INIT |
| 185 | |
| 186 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 187 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ |
| 188 | |
| 189 | /* |
| 190 | * External Bus Controller (EBC) Setup |
| 191 | */ |
| 192 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
| 193 | |
| 194 | /* Memory Bank 0 (NOR-FLASH) initialization */ |
| 195 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
| 196 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) |
| 197 | |
| 198 | #endif /* __CONFIG_H */ |