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git01.mediatek.com / filogic / uboot / 17c0dba8a69220912edab3b6c54c1781f792aa24 / . / drivers / watchdog / adi_wdt.c
blob: 6f5b3d5d04201a574e370bcadd79c6f223ed824f [file] [log] [blame]
Nathan Barrett-Morrison5724a9d2025-02-26 12:30:30 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * (C) Copyright 2022 - Analog Devices, Inc.
4 *
5 * Written and/or maintained by Timesys Corporation
6 *
7 * Converted to driver model by Nathan Barrett-Morrison
8 *
9 * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
10 * Contact: Greg Malysa <greg.malysa@timesys.com>
11 *
12 * adi_wtd.c - driver for ADI on-chip watchdog
13 *
14 */
15
16#include <clk.h>
17#include <dm.h>
18#include <wdt.h>
19#include <linux/delay.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22
23#define WDOG_CTL 0x0
24#define WDOG_CNT 0x4
25#define WDOG_STAT 0x8
26
27#define RCU_CTL 0x0
28#define RCU_STAT 0x4
29
30#define SEC_GCTL 0x0
31#define SEC_FCTL 0x10
32#define SEC_SCTL0 0x800
33
34#define WDEN 0x0010
35#define WDDIS 0x0AD0
36
37struct adi_wdt_priv {
38 void __iomem *rcu_base;
39 void __iomem *sec_base;
40 void __iomem *wdt_base;
41 struct clk clock;
42};
43
44static int adi_wdt_reset(struct udevice *dev)
45{
46 struct adi_wdt_priv *priv = dev_get_priv(dev);
47
48 iowrite32(0, priv->wdt_base + WDOG_STAT);
49
50 return 0;
51}
52
53static int adi_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
54{
55 struct adi_wdt_priv *priv = dev_get_priv(dev);
56
57 /* Disable SYSCD_RESETb input and clear the RCU0 reset status */
58 iowrite32(0xf, priv->rcu_base + RCU_STAT);
59 iowrite32(0x0, priv->rcu_base + RCU_CTL);
60
61 /* reset the SEC controller */
62 iowrite32(0x2, priv->sec_base + SEC_GCTL);
63 iowrite32(0x2, priv->sec_base + SEC_FCTL);
64
65 udelay(50);
66
67 /* enable SEC fault event */
68 iowrite32(0x1, priv->sec_base + SEC_GCTL);
69
70 /* ANOMALY 36100004 Spurious External Fault event occurs when FCTL
71 * is re-programmed when currently active fault is not cleared
72 */
73 iowrite32(0xc0, priv->sec_base + SEC_FCTL);
74 iowrite32(0xc1, priv->sec_base + SEC_FCTL);
75
76 /* enable SEC fault source for watchdog0 */
77 setbits_32(priv->sec_base + SEC_SCTL0 + (3*8), 0x6);
78
79 /* Enable SYSCD_RESETb input */
80 iowrite32(0x100, priv->rcu_base + RCU_CTL);
81
82 /* enable watchdog0 */
83 iowrite32(WDDIS, priv->wdt_base + WDOG_CTL);
84
85 iowrite32(timeout_ms / 1000 *
86 (clk_get_rate(&priv->clock) / (IS_ENABLED(CONFIG_SC58X) ? 2 : 1)),
87 priv->wdt_base + WDOG_CNT);
88
89 iowrite32(0, priv->wdt_base + WDOG_STAT);
90 iowrite32(WDEN, priv->wdt_base + WDOG_CTL);
91
92 return 0;
93}
94
95static int adi_wdt_probe(struct udevice *dev)
96{
97 struct adi_wdt_priv *priv = dev_get_priv(dev);
98 int ret;
99 struct resource res;
100
101 ret = dev_read_resource_byname(dev, "rcu", &res);
102 if (ret)
103 return ret;
104 priv->rcu_base = devm_ioremap(dev, res.start, resource_size(&res));
105
106 ret = dev_read_resource_byname(dev, "sec", &res);
107 if (ret)
108 return ret;
109 priv->sec_base = devm_ioremap(dev, res.start, resource_size(&res));
110
111 ret = dev_read_resource_byname(dev, "wdt", &res);
112 if (ret)
113 return ret;
114 priv->wdt_base = devm_ioremap(dev, res.start, resource_size(&res));
115
116 ret = clk_get_by_name(dev, "sclk0", &priv->clock);
117 if (ret < 0) {
118 printf("Can't get WDT clk: %d\n", ret);
119 return ret;
120 }
121
122 return 0;
123}
124
125static const struct wdt_ops adi_wdt_ops = {
126 .start = adi_wdt_start,
127 .reset = adi_wdt_reset,
128};
129
130static const struct udevice_id adi_wdt_ids[] = {
131 { .compatible = "adi,wdt" },
132 {}
133};
134
135U_BOOT_DRIVER(adi_wdt) = {
136 .name = "adi_wdt",
137 .id = UCLASS_WDT,
138 .of_match = adi_wdt_ids,
139 .probe = adi_wdt_probe,
140 .ops = &adi_wdt_ops,
141 .priv_auto = sizeof(struct adi_wdt_priv),
142 .flags = DM_FLAG_PRE_RELOC,
143};