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git01.mediatek.com / filogic / uboot / 17c0dba8a69220912edab3b6c54c1781f792aa24 / . / drivers / ddr / altera / iossm_mailbox.h
blob: 6f794781d30b71d7604363529ea8081bec4c0138 [file] [log] [blame]
Tingting Menga1a24f12025-02-21 21:49:41 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2025 Altera Corporation <www.altera.com>
4 *
5 */
6
7#define MAX_IO96B_SUPPORTED 2
8#define MAX_MEM_INTERFACE_SUPPORTED 2
9#define NUM_CMD_RESPONSE_DATA 3
10#define NUM_CMD_PARAM 7
11
12/* supported mailbox command type */
13enum iossm_mailbox_cmd_type {
14 CMD_NOP,
15 CMD_GET_SYS_INFO,
16 CMD_GET_MEM_INFO,
17 CMD_GET_MEM_CAL_INFO,
18 CMD_TRIG_CONTROLLER_OP,
19 CMD_TRIG_MEM_CAL_OP
20};
21
22/* supported mailbox command opcode */
23enum iossm_mailbox_cmd_opcode {
24 ECC_ENABLE_SET = 0x0101,
25 ECC_INTERRUPT_MASK = 0x0105,
26 ECC_WRITEBACK_ENABLE = 0x0106,
27 ECC_INJECT_ERROR = 0x0109,
28 ECC_SCRUB_MODE_0_START = 0x0202,
29 ECC_SCRUB_MODE_1_START = 0x0203,
30 BIST_STANDARD_MODE_START = 0x0301,
31 BIST_MEM_INIT_START = 0x0303,
32 BIST_SET_DATA_PATTERN_UPPER = 0x0305,
33 BIST_SET_DATA_PATTERN_LOWER = 0x0306,
34 TRIG_MEM_CAL = 0x000a
35};
36
37/*
38 * IOSSM mailbox required information
39 *
40 * @num_mem_interface: Number of memory interfaces instantiated
41 * @ip_type: IP type implemented on the IO96B
42 * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B
43 */
44struct io96b_mb_ctrl {
45 u32 num_mem_interface;
46 u32 ip_type[2];
47 u32 ip_id[2];
48};
49
50/* CMD_REQ Register Definition */
51#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29)
52#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24)
53#define CMD_TYPE_MASK GENMASK(23, 16)
54#define CMD_OPCODE_MASK GENMASK(15, 0)
55
56/*
57 * IOSSM mailbox request
58 * @ip_type: IP type for the specified memory interface
59 * @ip_id: IP instance ID for the specified memory interface
60 * @usr_cmd_type: User desire IOSSM mailbox command type
61 * @usr_cmd_opcode: User desire IOSSM mailbox command opcode
62 * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command
63 */
64struct io96b_mb_req {
65 u32 ip_type;
66 u32 ip_id;
67 u32 usr_cmd_type;
68 u32 usr_cmd_opcode;
69 u32 cmd_param[NUM_CMD_PARAM];
70};
71
72/*
73 * IOSSM mailbox response outputs
74 *
75 * @cmd_resp_status: Command Interface status
76 * @cmd_resp_data_*: More spaces for command response
77 */
78struct io96b_mb_resp {
79 u32 cmd_resp_status;
80 u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA];
81};
82
83/*
84 * IO96B instance specific information
85 *
86 * @size: Memory size
87 * @io96b_csr_addr: IO96B instance CSR address
88 * @cal_status: IO96B instance calibration status
89 * @mb_ctrl: IOSSM mailbox required information
90 */
91struct io96b_instance {
92 u16 size;
93 phys_addr_t io96b_csr_addr;
94 bool cal_status;
95 struct io96b_mb_ctrl mb_ctrl;
96};
97
98/*
99 * Overall IO96B instance(s) information
100 *
101 * @num_instance: Number of instance(s) assigned to HPS
102 * @overall_cal_status: Overall calibration status for all IO96B instance(s)
103 * @ddr_type: DDR memory type
104 * @ecc_status: ECC enable status (false = disabled, true = enabled)
105 * @overall_size: Total DDR memory size
106 * @io96b[]: IO96B instance specific information
107 * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked)
108 * @num_port: Number of IO96B port.
109 * @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected,
110 * bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected,
111 * bit 3: EMIF1 PLL B selected
112 */
113struct io96b_info {
114 u8 num_instance;
115 bool overall_cal_status;
116 const char *ddr_type;
117 bool ecc_status;
118 u16 overall_size;
119 struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
120 bool ckgen_lock;
121 u8 num_port;
122 u8 io96b_pll;
123};
124
125int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
126 u32 resp_data_len, struct io96b_mb_resp *resp);
127
128/* Supported IOSSM mailbox function */
129void io96b_mb_init(struct io96b_info *io96b_ctrl);
130int io96b_cal_status(phys_addr_t addr);
131void init_mem_cal(struct io96b_info *io96b_ctrl);
132int get_mem_technology(struct io96b_info *io96b_ctrl);
133int get_mem_width_info(struct io96b_info *io96b_ctrl);
134int ecc_enable_status(struct io96b_info *io96b_ctrl);
135int bist_mem_init_start(struct io96b_info *io96b_ctrl);
136bool ecc_interrupt_status(struct io96b_info *io96b_ctrl);