Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2011 Samsung Electronics |
| 4 | * |
Chander Kashyap | 4131a77 | 2011-12-06 23:34:12 +0000 | [diff] [blame] | 5 | * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
Piotr Wilczek | eb68f44 | 2014-03-07 14:59:46 +0100 | [diff] [blame] | 8 | #ifndef __CONFIG_ORIGEN_H |
| 9 | #define __CONFIG_ORIGEN_H |
| 10 | |
Simon Glass | be16500 | 2014-10-07 22:01:44 -0600 | [diff] [blame] | 11 | #include <configs/exynos4-common.h> |
Piotr Wilczek | eb68f44 | 2014-03-07 14:59:46 +0100 | [diff] [blame] | 12 | |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 13 | /* High Level Configuration Options */ |
Chander Kashyap | 4131a77 | 2011-12-06 23:34:12 +0000 | [diff] [blame] | 14 | #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 15 | #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ |
| 16 | |
Piotr Wilczek | eb68f44 | 2014-03-07 14:59:46 +0100 | [diff] [blame] | 17 | /* ORIGEN has 4 bank of DRAM */ |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 18 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
Piotr Wilczek | eb68f44 | 2014-03-07 14:59:46 +0100 | [diff] [blame] | 19 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
| 20 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 21 | |
Piotr Wilczek | eb68f44 | 2014-03-07 14:59:46 +0100 | [diff] [blame] | 22 | /* Power Down Modes */ |
| 23 | #define S5P_CHECK_SLEEP 0x00000BAD |
| 24 | #define S5P_CHECK_DIDLE 0xBAD00000 |
| 25 | #define S5P_CHECK_LPA 0xABAD0000 |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 26 | |
Chander Kashyap | 488ef1a | 2011-08-18 22:37:20 +0000 | [diff] [blame] | 27 | /* MMC SPL */ |
Chander Kashyap | 488ef1a | 2011-08-18 22:37:20 +0000 | [diff] [blame] | 28 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
Inderpal Singh | 4a699c7 | 2013-04-04 23:09:21 +0000 | [diff] [blame] | 29 | |
Guillaume GARDET | 0df3a9d | 2014-10-08 15:04:38 +0200 | [diff] [blame] | 30 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 31 | "loadaddr=0x40007000\0" \ |
| 32 | "rdaddr=0x48000000\0" \ |
| 33 | "kerneladdr=0x40007000\0" \ |
| 34 | "ramdiskaddr=0x48000000\0" \ |
| 35 | "console=ttySAC2,115200n8\0" \ |
| 36 | "mmcdev=0\0" \ |
| 37 | "bootenv=uEnv.txt\0" \ |
| 38 | "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ |
| 39 | "importbootenv=echo Importing environment from mmc ...; " \ |
| 40 | "env import -t $loadaddr $filesize\0" \ |
| 41 | "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
| 42 | "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ |
| 43 | "source ${loadaddr}\0" |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 44 | |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 45 | /* MIU (Memory Interleaving Unit) */ |
| 46 | #define CONFIG_MIU_2BIT_21_7_INTERLEAVED |
| 47 | |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 48 | #define RESERVE_BLOCK_SIZE (512) |
| 49 | #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 50 | |
Chander Kashyap | 0e7ab68 | 2011-08-18 22:37:19 +0000 | [diff] [blame] | 51 | #endif /* __CONFIG_H */ |