blob: 84e5d5df38dfc18db8f659a6c3a6d6ba26c9a811 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liuf13321d2014-03-05 15:04:48 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Yangbo Lubb32e682021-06-03 10:51:19 +08004 * Copyright 2020-2021 NXP
Shengzhou Liuf13321d2014-03-05 15:04:48 +08005 */
6
7/*
8 * T2080 RDB/PCIe board configuration file
9 */
10
11#ifndef __T2080RDB_H
12#define __T2080RDB_H
13
Simon Glassfb64e362020-05-10 11:40:09 -060014#include <linux/stringify.h>
15
Shengzhou Liuf13321d2014-03-05 15:04:48 +080016#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
Shengzhou Liuf13321d2014-03-05 15:04:48 +080017#define CONFIG_FSL_SATA_V2
18
19/* High Level Configuration Options */
Shengzhou Liuf13321d2014-03-05 15:04:48 +080020#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Shengzhou Liuf13321d2014-03-05 15:04:48 +080021#define CONFIG_ENABLE_36BIT_PHYS
22
Shengzhou Liuf13321d2014-03-05 15:04:48 +080023#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sunfe845072016-12-28 08:43:45 -080024#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Shengzhou Liuf13321d2014-03-05 15:04:48 +080025
26#ifdef CONFIG_RAMBOOT_PBL
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080027#define RESET_VECTOR_OFFSET 0x27FFC
28#define BOOT_PAGE_OFFSET 0x27000
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080029
Miquel Raynald0935362019-10-03 19:50:03 +020030#ifdef CONFIG_MTD_RAW_NAND
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080031#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
32#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
33#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
Pali Rohár7e814162022-04-25 14:21:20 +053034#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
35#define CONFIG_SYS_MPC85XX_NO_RESETVEC
36#endif
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080037#endif
38
39#ifdef CONFIG_SPIFLASH
40#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080041#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
42#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
43#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
44#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080045#ifndef CONFIG_SPL_BUILD
46#define CONFIG_SYS_MPC85XX_NO_RESETVEC
47#endif
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080048#endif
49
50#ifdef CONFIG_SDCARD
51#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080052#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
53#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
54#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
55#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080056#ifndef CONFIG_SPL_BUILD
57#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Shengzhou Liuf13321d2014-03-05 15:04:48 +080058#endif
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080059#endif
60
61#endif /* CONFIG_RAMBOOT_PBL */
Shengzhou Liuf13321d2014-03-05 15:04:48 +080062
63#define CONFIG_SRIO_PCIE_BOOT_MASTER
64#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
65/* Set 1M boot space */
66#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
67#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
68 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
69#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shengzhou Liuf13321d2014-03-05 15:04:48 +080070#endif
71
Shengzhou Liuf13321d2014-03-05 15:04:48 +080072#ifndef CONFIG_RESET_VECTOR_ADDRESS
73#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
74#endif
75
76/*
77 * These can be toggled for performance analysis, otherwise use default.
78 */
79#define CONFIG_SYS_CACHE_STASHING
Shengzhou Liuf13321d2014-03-05 15:04:48 +080080#ifdef CONFIG_DDR_ECC
Shengzhou Liuf13321d2014-03-05 15:04:48 +080081#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
82#endif
83
Shengzhou Liuf13321d2014-03-05 15:04:48 +080084/*
85 * Config the L3 Cache as L3 SRAM
86 */
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080087#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
88#define CONFIG_SYS_L3_SIZE (512 << 10)
Tom Rini5cd7ece2019-11-18 20:02:10 -050089#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
Shengzhou Liuf13321d2014-03-05 15:04:48 +080090
91#define CONFIG_SYS_DCSRBAR 0xf0000000
92#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
93
94/* EEPROM */
Shengzhou Liuf13321d2014-03-05 15:04:48 +080095#define CONFIG_SYS_I2C_EEPROM_NXID
96#define CONFIG_SYS_EEPROM_BUS_NUM 0
Shengzhou Liuf13321d2014-03-05 15:04:48 +080097
98/*
99 * DDR Setup
100 */
101#define CONFIG_VERY_BIG_RAM
102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800104#define CONFIG_SYS_SPD_BUS_NUM 0
105#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
106#define SPD_EEPROM_ADDRESS1 0x51
107#define SPD_EEPROM_ADDRESS2 0x52
108#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
109#define CTRL_INTLV_PREFERED cacheline
110
111/*
112 * IFC Definitions
113 */
114#define CONFIG_SYS_FLASH_BASE 0xe8000000
115#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
116#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
117#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
118 CSPR_PORT_SIZE_16 | \
119 CSPR_MSEL_NOR | \
120 CSPR_V)
121#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
122
123/* NOR Flash Timing Params */
124#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
125
126#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
127 FTIM0_NOR_TEADC(0x5) | \
128 FTIM0_NOR_TEAHC(0x5))
129#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
130 FTIM1_NOR_TRAD_NOR(0x1A) |\
131 FTIM1_NOR_TSEQRAD_NOR(0x13))
132#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
133 FTIM2_NOR_TCH(0x4) | \
134 FTIM2_NOR_TWPH(0x0E) | \
135 FTIM2_NOR_TWP(0x1c))
136#define CONFIG_SYS_NOR_FTIM3 0x0
137
138#define CONFIG_SYS_FLASH_QUIET_TEST
139#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800141#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
142#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144#define CONFIG_SYS_FLASH_EMPTY_INFO
145#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
146
147/* CPLD on IFC */
148#define CONFIG_SYS_CPLD_BASE 0xffdf0000
149#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
150#define CONFIG_SYS_CSPR2_EXT (0xf)
151#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
152 | CSPR_PORT_SIZE_8 \
153 | CSPR_MSEL_GPCM \
154 | CSPR_V)
155#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
156#define CONFIG_SYS_CSOR2 0x0
157
158/* CPLD Timing parameters for IFC CS2 */
159#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
160 FTIM0_GPCM_TEADC(0x0e) | \
161 FTIM0_GPCM_TEAHC(0x0e))
162#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
163 FTIM1_GPCM_TRAD(0x1f))
164#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiec2bc4602014-06-26 14:41:33 +0800165 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800166 FTIM2_GPCM_TWP(0x1f))
167#define CONFIG_SYS_CS2_FTIM3 0x0
168
169/* NAND Flash on IFC */
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800170#define CONFIG_SYS_NAND_BASE 0xff800000
171#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
172
173#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
174#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
175 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
176 | CSPR_MSEL_NAND /* MSEL = NAND */ \
177 | CSPR_V)
178#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
179
180#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
181 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
182 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
183 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
184 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
185 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
186 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
187
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800188/* ONFI NAND Flash mode0 Timing Params */
189#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
190 FTIM0_NAND_TWP(0x18) | \
191 FTIM0_NAND_TWCHT(0x07) | \
192 FTIM0_NAND_TWH(0x0a))
193#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
194 FTIM1_NAND_TWBE(0x39) | \
195 FTIM1_NAND_TRR(0x0e) | \
196 FTIM1_NAND_TRP(0x18))
197#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
198 FTIM2_NAND_TREH(0x0a) | \
199 FTIM2_NAND_TWHRE(0x1e))
200#define CONFIG_SYS_NAND_FTIM3 0x0
201
202#define CONFIG_SYS_NAND_DDR_LAW 11
203#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
204#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800205
Miquel Raynald0935362019-10-03 19:50:03 +0200206#if defined(CONFIG_MTD_RAW_NAND)
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800207#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
208#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
209#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
210#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
211#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
212#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
213#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
214#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
215#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
216#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
217#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
218#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
219#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
220#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
221#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
222#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
223#else
224#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
225#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
226#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
227#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
228#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
229#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
230#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
231#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
232#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
233#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
234#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
235#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
236#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
237#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
238#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
239#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
240#endif
241
242#if defined(CONFIG_RAMBOOT_PBL)
243#define CONFIG_SYS_RAMBOOT
244#endif
245
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800246#define CONFIG_HWCONFIG
247
248/* define to use L1 as initial stack */
249#define CONFIG_L1_INIT_RAM
250#define CONFIG_SYS_INIT_RAM_LOCK
251#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
252#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunee7b4832015-08-17 13:31:51 -0700253#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800254/* The assembler doesn't like typecast */
255#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
256 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
257 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
258#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Tom Rini55f37562022-05-24 14:14:02 -0400259#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530260#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800261
262/*
263 * Serial Port
264 */
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800265#define CONFIG_SYS_NS16550_SERIAL
266#define CONFIG_SYS_NS16550_REG_SIZE 1
267#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
268#define CONFIG_SYS_BAUDRATE_TABLE \
269 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
270#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
271#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
272#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
273#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
274
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800275/*
276 * I2C
277 */
Biwen Li07b3dcf2020-05-01 20:04:19 +0800278
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800279#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
280#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
281#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
282#define I2C_MUX_CH_DEFAULT 0x8
283
Ying Zhang3861e822015-03-10 14:21:36 +0800284#define I2C_MUX_CH_VOL_MONITOR 0xa
285
Ying Zhang3861e822015-03-10 14:21:36 +0800286/* The lowest and highest voltage allowed for T208xRDB */
287#define VDD_MV_MIN 819
288#define VDD_MV_MAX 1212
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800289
290/*
291 * RapidIO
292 */
293#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
294#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
295#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
296#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
297#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
298#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
299/*
300 * for slave u-boot IMAGE instored in master memory space,
301 * PHYS must be aligned based on the SIZE
302 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800303#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
304#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
305#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
306#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800307/*
308 * for slave UCODE and ENV instored in master memory space,
309 * PHYS must be aligned based on the SIZE
310 */
Liu Gang416dbfe2014-05-15 14:30:34 +0800311#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800312#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
313#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
314
315/* slave core release by master*/
316#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
317#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
318
319/*
320 * SRIO_PCIE_BOOT - SLAVE
321 */
322#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
323#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
324#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
325 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
326#endif
327
328/*
329 * eSPI - Enhanced SPI
330 */
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800331
332/*
333 * General PCI
334 * Memory space is mapped 1-1, but I/O space must start from 0.
335 */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400336#define CONFIG_PCIE1 /* PCIE controller 1 */
337#define CONFIG_PCIE2 /* PCIE controller 2 */
338#define CONFIG_PCIE3 /* PCIE controller 3 */
339#define CONFIG_PCIE4 /* PCIE controller 4 */
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800340/* controller 1, direct to uli, tgtid 3, Base address 20000 */
341#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800342#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800343#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800344#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800345
346/* controller 2, Slot 2, tgtid 2, Base address 201000 */
347#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800348#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800349#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800350#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800351
352/* controller 3, Slot 1, tgtid 1, Base address 202000 */
353#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800354#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800355#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800356#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800357
358/* controller 4, Base address 203000 */
359#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800360#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800361#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800362
363#ifdef CONFIG_PCI
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800364#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800365#endif
366
367/* Qman/Bman */
368#ifndef CONFIG_NOBQFMAN
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800369#define CONFIG_SYS_BMAN_NUM_PORTALS 18
370#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
371#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
372#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500373#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
374#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
375#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
376#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
377#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
378 CONFIG_SYS_BMAN_CENA_SIZE)
379#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
380#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800381#define CONFIG_SYS_QMAN_NUM_PORTALS 18
382#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
383#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
384#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceurff2c6462014-12-08 14:54:01 -0500385#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
386#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
387#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
388#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
389#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
390 CONFIG_SYS_QMAN_CENA_SIZE)
391#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
392#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800393
394#define CONFIG_SYS_DPAA_FMAN
395#define CONFIG_SYS_DPAA_PME
396#define CONFIG_SYS_PMAN
397#define CONFIG_SYS_DPAA_DCE
398#define CONFIG_SYS_DPAA_RMAN /* RMan */
399#define CONFIG_SYS_INTERLAKEN
400
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800401#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
402#endif /* CONFIG_NOBQFMAN */
403
404#ifdef CONFIG_SYS_DPAA_FMAN
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800405#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
406#define RGMII_PHY2_ADDR 0x02
407#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
408#define CORTINA_PHY_ADDR2 0x0d
Camelia Grozaec69c692021-06-16 17:47:31 +0530409/* Aquantia AQ1202 10G Base-T used by board revisions up to C */
410#define FM1_10GEC3_PHY_ADDR 0x00
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800411#define FM1_10GEC4_PHY_ADDR 0x01
Camelia Grozaec69c692021-06-16 17:47:31 +0530412/* Aquantia AQR113C 10G Base-T used by board revisions D and up */
413#define AQR113C_PHY_ADDR1 0x00
414#define AQR113C_PHY_ADDR2 0x08
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800415#endif
416
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800417/*
418 * SATA
419 */
420#ifdef CONFIG_FSL_SATA_V2
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800421#define CONFIG_SATA1
422#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
423#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
424#define CONFIG_SATA2
425#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
426#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
427#define CONFIG_LBA48
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800428#endif
429
430/*
431 * USB
432 */
Tom Riniceed5d22017-05-12 22:33:27 -0400433#ifdef CONFIG_USB_EHCI_HCD
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800434#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800435#define CONFIG_HAS_FSL_DR_USB
436#endif
437
438/*
439 * SDHC
440 */
441#ifdef CONFIG_MMC
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800442#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
443#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800444#endif
445
446/*
Shengzhou Liu7410e2b2014-04-02 14:28:35 +0800447 * Dynamic MTD Partition support with mtdparts
448 */
Shengzhou Liu7410e2b2014-04-02 14:28:35 +0800449
450/*
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800451 * Environment
452 */
453
454/*
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800455 * Miscellaneous configurable options
456 */
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800457
458/*
459 * For booting Linux, the board info and command line data
460 * have to be in the first 64 MB of memory, since this is
461 * the maximum mapped by the Linux kernel during initialization.
462 */
463#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
464#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
465
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800466/*
467 * Environment Configuration
468 */
469#define CONFIG_ROOTPATH "/opt/nfsroot"
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800470#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
471
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800472#define __USB_PHY_TYPE utmi
473
474#define CONFIG_EXTRA_ENV_SETTINGS \
475 "hwconfig=fsl_ddr:" \
476 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
477 "bank_intlv=auto;" \
478 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
479 "netdev=eth0\0" \
480 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
481 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
482 "tftpflash=tftpboot $loadaddr $uboot && " \
483 "protect off $ubootaddr +$filesize && " \
484 "erase $ubootaddr +$filesize && " \
485 "cp.b $loadaddr $ubootaddr $filesize && " \
486 "protect on $ubootaddr +$filesize && " \
487 "cmp.b $loadaddr $ubootaddr $filesize\0" \
488 "consoledev=ttyS0\0" \
489 "ramdiskaddr=2000000\0" \
490 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500491 "fdtaddr=1e00000\0" \
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800492 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
Kim Phillips1dedccc2014-05-14 19:33:45 -0500493 "bdev=sda3\0"
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800494
495/*
496 * For emulation this causes u-boot to jump to the start of the
497 * proof point app code automatically
498 */
Tom Rini9aed2af2021-08-19 14:29:00 -0400499#define PROOF_POINTS \
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800500 "setenv bootargs root=/dev/$bdev rw " \
501 "console=$consoledev,$baudrate $othbootargs;" \
502 "cpu 1 release 0x29000000 - - -;" \
503 "cpu 2 release 0x29000000 - - -;" \
504 "cpu 3 release 0x29000000 - - -;" \
505 "cpu 4 release 0x29000000 - - -;" \
506 "cpu 5 release 0x29000000 - - -;" \
507 "cpu 6 release 0x29000000 - - -;" \
508 "cpu 7 release 0x29000000 - - -;" \
509 "go 0x29000000"
510
Tom Rini9aed2af2021-08-19 14:29:00 -0400511#define HVBOOT \
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800512 "setenv bootargs config-addr=0x60000000; " \
513 "bootm 0x01000000 - 0x00f00000"
514
Tom Rini9aed2af2021-08-19 14:29:00 -0400515#define ALU \
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800516 "setenv bootargs root=/dev/$bdev rw " \
517 "console=$consoledev,$baudrate $othbootargs;" \
518 "cpu 1 release 0x01000000 - - -;" \
519 "cpu 2 release 0x01000000 - - -;" \
520 "cpu 3 release 0x01000000 - - -;" \
521 "cpu 4 release 0x01000000 - - -;" \
522 "cpu 5 release 0x01000000 - - -;" \
523 "cpu 6 release 0x01000000 - - -;" \
524 "cpu 7 release 0x01000000 - - -;" \
525 "go 0x01000000"
526
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800527#include <asm/fsl_secure_boot.h>
Aneesh Bansal962021a2016-01-22 16:37:22 +0530528
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800529#endif /* __T2080RDB_H */