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git01.mediatek.com / filogic / uboot / 177fdde3b4f1e82b7ef5d510916bb20c62d27ad7 / . / include / configs / lwmon5.h
blob: c4b7c4ee504196abacaad0b4e284f909ca3cd5b4 [file] [log] [blame]
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/************************************************************************
22 * lwmon5.h - configuration for lwmon5 board
23 ***********************************************************************/
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30#define CONFIG_LWMON5 1 /* Board is lwmon5 */
31#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roesee83ffdf2007-06-15 11:33:41 +0200[diff] [blame]32#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]33#define CONFIG_4xx 1 /* ... PPC4xx family */
34#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
35
36#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
38#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
39
40/*-----------------------------------------------------------------------
41 * Base addresses -- Note these are effective addresses where the
42 * actual resources get mapped (not physical addresses)
43 *----------------------------------------------------------------------*/
44#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
45#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
46
47#define CFG_BOOT_BASE_ADDR 0xf0000000
48#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
49#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
50#define CFG_MONITOR_BASE TEXT_BASE
51#define CFG_LIME_BASE_0 0xc0000000
52#define CFG_LIME_BASE_1 0xc1000000
53#define CFG_LIME_BASE_2 0xc2000000
54#define CFG_LIME_BASE_3 0xc3000000
55#define CFG_FPGA_BASE_0 0xc4000000
56#define CFG_FPGA_BASE_1 0xc4200000
57#define CFG_OCM_BASE 0xe0010000 /* ocm */
58#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
59#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
61#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
62#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
63
64/* Don't change either of these */
65#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
66
67#define CFG_USB2D0_BASE 0xe0000100
68#define CFG_USB_DEVICE 0xe0000000
69#define CFG_USB_HOST 0xe0000400
70
71/*-----------------------------------------------------------------------
72 * Initial RAM & stack pointer
73 *----------------------------------------------------------------------*/
74/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
75#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
76#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
77
78#define CFG_INIT_RAM_END (4 << 10)
79#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
80#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
81#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
82
83/*-----------------------------------------------------------------------
84 * Serial Port
85 *----------------------------------------------------------------------*/
86#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
87#define CONFIG_BAUDRATE 115200
88#define CONFIG_SERIAL_MULTI 1
89/* define this if you want console on UART1 */
90#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
91
92#define CFG_BAUDRATE_TABLE \
93 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
94
95/*-----------------------------------------------------------------------
96 * Environment
97 *----------------------------------------------------------------------*/
98#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
99
100/*-----------------------------------------------------------------------
101 * FLASH related
102 *----------------------------------------------------------------------*/
103#define CFG_FLASH_CFI /* The flash is CFI compatible */
104#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
105
106#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
107
108#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
109#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
110
111#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
112#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
113
114#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
115#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
116
117#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
118#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
119
Wolfgang Denk70df7bc2007-06-22 23:59:00 +0200[diff] [blame]120#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]121#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
122#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
123
124/* Address and size of Redundant Environment Sector */
125#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
126#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
127
128/*-----------------------------------------------------------------------
129 * DDR SDRAM
130 *----------------------------------------------------------------------*/
131#define CFG_MBYTES_SDRAM (256) /* 256MB */
132#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
133#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
134#if 0 /* test-only: disable ECC for now */
135#define CONFIG_DDR_ECC 1 /* enable ECC */
136#endif
137
138/*-----------------------------------------------------------------------
139 * I2C
140 *----------------------------------------------------------------------*/
141#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
142#undef CONFIG_SOFT_I2C /* I2C bit-banged */
143#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
144#define CFG_I2C_SLAVE 0x7F
145
146#define CFG_I2C_MULTI_EEPROMS
147#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
148#define CFG_I2C_EEPROM_ADDR_LEN 1
149#define CFG_EEPROM_PAGE_WRITE_ENABLE
150#define CFG_EEPROM_PAGE_WRITE_BITS 3
151#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
152
153#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
154#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
155
156#define CONFIG_PREBOOT "echo;" \
157 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
158 "echo"
159
160#undef CONFIG_BOOTARGS
161
162#define CONFIG_EXTRA_ENV_SETTINGS \
163 "hostname=lwmon5\0" \
164 "netdev=eth0\0" \
Stefan Roesef8616312007-07-06 11:48:24 +0200[diff] [blame]165 "unlock=yes\0" \
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]166 "nfsargs=setenv bootargs root=/dev/nfs rw " \
167 "nfsroot=${serverip}:${rootpath}\0" \
168 "ramargs=setenv bootargs root=/dev/ram rw\0" \
169 "addip=setenv bootargs ${bootargs} " \
170 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
171 ":${hostname}:${netdev}:off panic=1\0" \
172 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
173 "flash_nfs=run nfsargs addip addtty;" \
174 "bootm ${kernel_addr}\0" \
175 "flash_self=run ramargs addip addtty;" \
176 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
177 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
178 "bootm\0" \
179 "rootpath=/opt/eldk/ppc_4xxFP\0" \
180 "bootfile=/tftpboot/lwmon5/uImage\0" \
181 "kernel_addr=FC000000\0" \
182 "ramdisk_addr=FC180000\0" \
183 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
184 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
185 "cp.b 200000 FFF80000 80000\0" \
186 "upd=run load;run update\0" \
Stefan Roese177fdde2007-07-06 12:26:51 +0200[diff] [blame^]187 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
188 "autoscr 200000\0" \
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]189 ""
190#define CONFIG_BOOTCOMMAND "run flash_self"
191
192#if 0
193#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
194#else
195#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
196#endif
197
198#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
199#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
200
201#define CONFIG_IBM_EMAC4_V4 1
202#define CONFIG_MII 1 /* MII PHY management */
203#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
204
205#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
206
207#define CONFIG_HAS_ETH0
208#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
209
210#define CONFIG_NET_MULTI 1
211#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
212#define CONFIG_PHY1_ADDR 1
213
214/* USB */
215#ifdef CONFIG_440EPX
216#define CONFIG_USB_OHCI
217#define CONFIG_USB_STORAGE
218
219/* Comment this out to enable USB 1.1 device */
220#define USB_2_0_DEVICE
221
222#define CMD_USB CFG_CMD_USB
223#else
224#define CMD_USB 0 /* no USB on 440GRx */
225#endif /* CONFIG_440EPX */
226
227/* Partitions */
228#define CONFIG_MAC_PARTITION
229#define CONFIG_DOS_PARTITION
230#define CONFIG_ISO_PARTITION
231
232#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
233 CFG_CMD_ASKENV | \
234 CFG_CMD_DATE | \
235 CFG_CMD_DHCP | \
236 CFG_CMD_DIAG | \
237 CFG_CMD_EEPROM | \
238 CFG_CMD_ELF | \
239 CFG_CMD_FAT | \
240 CFG_CMD_I2C | \
241 CFG_CMD_IRQ | \
242 CFG_CMD_MII | \
243 CFG_CMD_NET | \
244 CFG_CMD_NFS | \
245 CFG_CMD_PCI | \
246 CFG_CMD_PING | \
247 CFG_CMD_REGINFO | \
248 CFG_CMD_SDRAM | \
249 CMD_USB)
250
251#define CONFIG_SUPPORT_VFAT
252
253/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
254#include <cmd_confdefs.h>
255
256/*-----------------------------------------------------------------------
257 * Miscellaneous configurable options
258 *----------------------------------------------------------------------*/
259#define CFG_LONGHELP /* undef to save memory */
260#define CFG_PROMPT "=> " /* Monitor Command Prompt */
261#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
262#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
263#else
264#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
265#endif
266#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
267#define CFG_MAXARGS 16 /* max number of command args */
268#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
269
270#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
271#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
272
273#define CFG_LOAD_ADDR 0x100000 /* default load address */
274#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
275
276#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
277
278#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
279#define CONFIG_LOOPW 1 /* enable loopw command */
280#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
281#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
282#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
283
284/*-----------------------------------------------------------------------
285 * PCI stuff
286 *----------------------------------------------------------------------*/
287/* General PCI */
288#define CONFIG_PCI /* include pci support */
289#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
290#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
291#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
292
293/* Board-specific PCI */
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]294#define CFG_PCI_TARGET_INIT
295#define CFG_PCI_MASTER_INIT
296
297#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
298#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
299
300#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
301
302/*
303 * For booting Linux, the board info and command line data
304 * have to be in the first 8 MB of memory, since this is
305 * the maximum mapped by the Linux kernel during initialization.
306 */
307#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
308
309/*-----------------------------------------------------------------------
310 * External Bus Controller (EBC) Setup
311 *----------------------------------------------------------------------*/
312#define CFG_FLASH CFG_FLASH_BASE
313
314/* Memory Bank 0 (NOR-FLASH) initialization */
315#define CFG_EBC_PB0AP 0x03050200
316#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000)
317
318/* Memory Bank 1 (Lime) initialization */
319#define CFG_EBC_PB1AP 0x01004380
320#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
321
322/* Memory Bank 2 (FPGA) initialization */
323#define CFG_EBC_PB2AP 0x01004400
324#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
325
326/* Memory Bank 3 (FPGA2) initialization */
327#define CFG_EBC_PB3AP 0x01004400
328#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
329
330#define CFG_EBC_CFG 0xb8400000
331
332/*-----------------------------------------------------------------------
Stefan Roesed11a5e22007-07-04 10:06:30 +0200[diff] [blame]333 * Graphics (Fujitsu Lime)
334 *----------------------------------------------------------------------*/
335/* SDRAM Clock frequency adjustment register */
336#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
337/* Lime Clock frequency is to set 133MHz */
338#define CFG_LIME_CLOCK_133MHZ 0x10000
339
340/* SDRAM Parameter register */
341#define CFG_LIME_MMR 0xC1FCFFFC
342/* SDRAM parameter value */
343#define CFG_LIME_MMR_VALUE 0x414FB7F2
344
345/*-----------------------------------------------------------------------
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]346 * GPIO Setup
347 *----------------------------------------------------------------------*/
348#define CFG_GPIO_PHY1_RST 12
349#define CFG_GPIO_FLASH_WP 14
350#define CFG_GPIO_PHY0_RST 22
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]351#define CFG_GPIO_WATCHDOG 58
352#define CFG_GPIO_LIME_S 59
353#define CFG_GPIO_LIME_RST 60
354
355/*-----------------------------------------------------------------------
356 * PPC440 GPIO Configuration
357 */
358#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
359{ \
360/* GPIO Core 0 */ \
361{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
362{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
363{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
364{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
365{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
366{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
367{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
368{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
369{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
370{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
371{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
372{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
373{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
374{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
375{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
376{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
Wolfgang Denk70df7bc2007-06-22 23:59:00 +0200[diff] [blame]377{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]378{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
379{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
380{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
381{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
382{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
383{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
384{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
385{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
386{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
387{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
388{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
389{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
390{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
391{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
392{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
393}, \
394{ \
395/* GPIO Core 1 */ \
396{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
397{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
398{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
399{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
400{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
401{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
402{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
403{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
404{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
405{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
406{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
407{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
408{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
409{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
410{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
411{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
412{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
413{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
Stefan Roesed11a5e22007-07-04 10:06:30 +0200[diff] [blame]414{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]415{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
416{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
417{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
418{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
419{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
420{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
421{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
422{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
423{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
424{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
425{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
426{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
427{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
428} \
429}
430
431/*-----------------------------------------------------------------------
432 * Cache Configuration
433 *----------------------------------------------------------------------*/
434#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
435#define CFG_CACHELINE_SIZE 32 /* ... */
436#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
437#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
438#endif
439
440/*
441 * Internal Definitions
442 *
443 * Boot Flags
444 */
445#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
446#define BOOTFLAG_WARM 0x02 /* Software reboot */
447
448#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
449#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
450#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
451#endif
452#endif /* __CONFIG_H */