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git01.mediatek.com / filogic / uboot / 1763b76cf9969d06e269bfc25209c52d94fa8352 / . / arch / arm / dts / tegra20-ventana.dts
blob: 851e0ed8d9a4b08f546bf1d5b088e2c772546668 [file] [log] [blame]
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6 model = "NVIDIA Tegra20 Ventana evaluation board";
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uartd;
11 };
12
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]13 aliases {
14 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]15 sdhci0 = "/sdhci@c8000600";
16 sdhci1 = "/sdhci@c8000400";
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]17 };
18
19 memory {
20 reg = <0x00000000 0x40000000>;
21 };
22
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]23 host1x@50000000 {
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]24 status = "okay";
25 dc@54200000 {
26 status = "okay";
27 rgb {
28 status = "okay";
29 nvidia,panel = <&lcd_panel>;
30 };
31 };
32 };
33
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]34 serial@70006300 {
35 clock-frequency = < 216000000 >;
36 };
37
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]38 usb@c5008000 {
39 status = "okay";
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]40 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]41
42 sdhci@c8000400 {
43 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]44 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
45 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
46 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]47 bus-width = <4>;
48 };
49
50 sdhci@c8000600 {
51 status = "okay";
52 bus-width = <8>;
53 };
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]54
Simon Glasse31a2a52016-01-30 16:37:52 -0700[diff] [blame]55 clocks {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 clk32k_in: clock@0 {
61 compatible = "fixed-clock";
62 reg=<0>;
63 #clock-cells = <0>;
64 clock-frequency = <32768>;
65 };
66 };
67
Simon Glassd8af3c92016-01-30 16:38:01 -0700[diff] [blame]68 pwm: pwm@7000a000 {
69 status = "okay";
70 };
71
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]72 lcd_panel: panel {
73 clock = <72072000>;
74 xres = <1366>;
75 yres = <768>;
76 left-margin = <58>;
77 right-margin = <58>;
78 hsync-len = <58>;
79 lower-margin = <4>;
80 upper-margin = <4>;
81 vsync-len = <4>;
82 hsync-active-high;
83 vsync-active-high;
84 nvidia,bits-per-pixel = <16>;
85 nvidia,pwm = <&pwm 2 0>;
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]86 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
87 GPIO_ACTIVE_HIGH>;
88 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
89 GPIO_ACTIVE_HIGH>;
90 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
91 GPIO_ACTIVE_HIGH>;
92 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
93 GPIO_ACTIVE_HIGH>;
Stephen Warrenc3836f32013-06-18 09:46:52 -0600[diff] [blame]94 nvidia,panel-timings = <0 0 200 0 0>;
95 };
Stephen Warren82252762012-05-23 07:46:15 +0000[diff] [blame]96};