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git01.mediatek.com / filogic / uboot / 173f642991a89f6c5ef8efd489c830653a669648 / . / dts / upstream / src / arm / nxp / imx / imx25-pdk.dts
blob: dd176fb54e58595b34a8cd2c35769f341729895a [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include "imx25.dtsi"
9
10/ {
11 model = "Freescale i.MX25 Product Development Kit";
12 compatible = "fsl,imx25-pdk", "fsl,imx25";
13
14 memory@80000000 {
15 device_type = "memory";
16 reg = <0x80000000 0x4000000>;
17 };
18
19 reg_fec_3v3: regulator-0 {
20 compatible = "regulator-fixed";
21 regulator-name = "fec-3v3";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio2 3 0>;
25 enable-active-high;
26 };
27
28 reg_2p5v: regulator-1 {
29 compatible = "regulator-fixed";
30 regulator-name = "2P5V";
31 regulator-min-microvolt = <2500000>;
32 regulator-max-microvolt = <2500000>;
33 };
34
35 reg_3p3v: regulator-2 {
36 compatible = "regulator-fixed";
37 regulator-name = "3P3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 };
41
42 reg_can_3v3: regulator-3 {
43 compatible = "regulator-fixed";
44 regulator-name = "can-3v3";
45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>;
47 gpio = <&gpio4 6 0>;
48 };
49
50 sound {
51 compatible = "fsl,imx25-pdk-sgtl5000",
52 "fsl,imx-audio-sgtl5000";
53 model = "imx25-pdk-sgtl5000";
54 ssi-controller = <&ssi1>;
55 audio-codec = <&codec>;
56 audio-routing =
57 "MIC_IN", "Mic Jack",
58 "Mic Jack", "Mic Bias",
59 "Headphone Jack", "HP_OUT";
60 mux-int-port = <1>;
61 mux-ext-port = <4>;
62 };
63
64 wvga: display {
65 model = "CLAA057VC01CW";
66 bits-per-pixel = <16>;
67 fsl,pcr = <0xfa208b80>;
68 bus-width = <18>;
69 display-timings {
70 native-mode = <&wvga_timings>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]71 wvga_timings: timing0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]72 hactive = <640>;
73 vactive = <480>;
74 hback-porch = <45>;
75 hfront-porch = <114>;
76 hsync-len = <1>;
77 vback-porch = <33>;
78 vfront-porch = <11>;
79 vsync-len = <1>;
80 clock-frequency = <25200000>;
81 };
82 };
83 };
84};
85
86&audmux {
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_audmux>;
89 status = "okay";
90};
91
92&can1 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_can1>;
95 xceiver-supply = <&reg_can_3v3>;
96 status = "okay";
97};
98
99&esdhc1 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_esdhc1>;
102 cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
103 wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
104 status = "okay";
105};
106
107&fec {
108 phy-mode = "rmii";
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_fec>;
111 phy-supply = <&reg_fec_3v3>;
112 phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
113 status = "okay";
114};
115
116&i2c1 {
117 clock-frequency = <100000>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_i2c1>;
120 status = "okay";
121
122 codec: sgtl5000@a {
123 compatible = "fsl,sgtl5000";
124 reg = <0x0a>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]125 #sound-dai-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]126 clocks = <&clks 129>;
127 VDDA-supply = <&reg_2p5v>;
128 VDDIO-supply = <&reg_3p3v>;
129 };
130};
131
132&iomuxc {
133 imx25-pdk {
134 pinctrl_audmux: audmuxgrp {
135 fsl,pins = <
136 MX25_PAD_RW__AUD4_TXFS 0xe0
137 MX25_PAD_OE__AUD4_TXC 0xe0
138 MX25_PAD_EB0__AUD4_TXD 0xe0
139 MX25_PAD_EB1__AUD4_RXD 0xe0
140 >;
141 };
142
143 pinctrl_can1: can1grp {
144 fsl,pins = <
145 MX25_PAD_GPIO_A__CAN1_TX 0x0
146 MX25_PAD_GPIO_B__CAN1_RX 0x0
147 MX25_PAD_D14__GPIO_4_6 0x80000000
148 >;
149 };
150
151 pinctrl_esdhc1: esdhc1grp {
152 fsl,pins = <
153 MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
154 MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
155 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
156 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
157 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
158 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
159 MX25_PAD_A14__GPIO_2_0 0x80000000
160 MX25_PAD_A15__GPIO_2_1 0x80000000
161 >;
162 };
163
164 pinctrl_fec: fecgrp {
165 fsl,pins = <
166 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
167 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
168 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
169 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
170 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
171 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
172 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
173 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
174 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
175 MX25_PAD_A17__GPIO_2_3 0x80000000
176 MX25_PAD_D12__GPIO_4_8 0x80000000
177 >;
178 };
179
180 pinctrl_i2c1: i2c1grp {
181 fsl,pins = <
182 MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
183 MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
184 >;
185 };
186
187 pinctrl_kpp: kppgrp {
188 fsl,pins = <
189 MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
190 MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
191 MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
192 MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
193 MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
194 MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
195 MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
196 MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
197 >;
198 };
199
200 pinctrl_lcd: lcdgrp {
201 fsl,pins = <
202 MX25_PAD_LD0__LD0 0xe0
203 MX25_PAD_LD1__LD1 0xe0
204 MX25_PAD_LD2__LD2 0xe0
205 MX25_PAD_LD3__LD3 0xe0
206 MX25_PAD_LD4__LD4 0xe0
207 MX25_PAD_LD5__LD5 0xe0
208 MX25_PAD_LD6__LD6 0xe0
209 MX25_PAD_LD7__LD7 0xe0
210 MX25_PAD_LD8__LD8 0xe0
211 MX25_PAD_LD9__LD9 0xe0
212 MX25_PAD_LD10__LD10 0xe0
213 MX25_PAD_LD11__LD11 0xe0
214 MX25_PAD_LD12__LD12 0xe0
215 MX25_PAD_LD13__LD13 0xe0
216 MX25_PAD_LD14__LD14 0xe0
217 MX25_PAD_LD15__LD15 0xe0
218 MX25_PAD_GPIO_E__LD16 0xe0
219 MX25_PAD_GPIO_F__LD17 0xe0
220 MX25_PAD_HSYNC__HSYNC 0xe0
221 MX25_PAD_VSYNC__VSYNC 0xe0
222 MX25_PAD_LSCLK__LSCLK 0xe0
223 MX25_PAD_OE_ACD__OE_ACD 0xe0
224 MX25_PAD_CONTRAST__CONTRAST 0xe0
225 >;
226 };
227
228 pinctrl_uart1: uart1grp {
229 fsl,pins = <
230 MX25_PAD_UART1_RTS__UART1_RTS 0xe0
231 MX25_PAD_UART1_CTS__UART1_CTS 0xe0
232 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
233 MX25_PAD_UART1_RXD__UART1_RXD 0xc0
234 >;
235 };
236 };
237};
238
239&lcdc {
240 display = <&wvga>;
241 fsl,lpccr = <0x00a903ff>;
242 fsl,lscr1 = <0x00120300>;
243 fsl,dmacr = <0x00020010>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_lcd>;
246 status = "okay";
247};
248
249&nfc {
250 nand-on-flash-bbt;
251 status = "okay";
252};
253
254&kpp {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_kpp>;
257 linux,keymap = <
258 MATRIX_KEY(0x0, 0x0, KEY_UP)
259 MATRIX_KEY(0x0, 0x1, KEY_DOWN)
260 MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
261 MATRIX_KEY(0x0, 0x3, KEY_HOME)
262 MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
263 MATRIX_KEY(0x1, 0x1, KEY_LEFT)
264 MATRIX_KEY(0x1, 0x2, KEY_ENTER)
265 MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
266 MATRIX_KEY(0x2, 0x0, KEY_F6)
267 MATRIX_KEY(0x2, 0x1, KEY_F8)
268 MATRIX_KEY(0x2, 0x2, KEY_F9)
269 MATRIX_KEY(0x2, 0x3, KEY_F10)
270 MATRIX_KEY(0x3, 0x0, KEY_F1)
271 MATRIX_KEY(0x3, 0x1, KEY_F2)
272 MATRIX_KEY(0x3, 0x2, KEY_F3)
273 MATRIX_KEY(0x3, 0x2, KEY_POWER)
274 >;
275 status = "okay";
276};
277
278&ssi1 {
279 status = "okay";
280};
281
282&tsc {
283 status = "okay";
284};
285
286&tscadc {
287 status = "okay";
288};
289
290&uart1 {
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_uart1>;
293 uart-has-rtscts;
294 status = "okay";
295};
296
297&usbhost1 {
298 status = "okay";
299};
300
301&usbotg {
302 external-vbus-divider;
303 status = "okay";
304};