| Jayesh Choudhary | 3aa5058 | 2024-06-14 18:14:37 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Keystone3 Quality of service endpoint definitions |
| 4 | * Auto generated by K3 Resource Partitioning Tool |
| 5 | * |
| 6 | * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #define PULSAR_SL_MCU_0_MEMBDG_RMST0 0x45D10000 |
| 10 | #define PULSAR_SL_MCU_0_MEMBDG_WMST0 0x45D10400 |
| 11 | #define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 |
| 12 | #define PULSAR_SL_MCU_0_MEMBDG_RMST1 0x45D11000 |
| 13 | #define PULSAR_SL_MCU_0_MEMBDG_WMST1 0x45D11400 |
| 14 | #define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 |
| 15 | #define SA2_UL_MCU_0_CTXCACH_EXT_DMA 0x45D13000 |
| 16 | #define ICSS_G_MAIN_0_PR1_EXT_VBUSM 0x45D80000 |
| 17 | #define ICSS_G_MAIN_1_PR1_EXT_VBUSM 0x45D80400 |
| 18 | #define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000 |
| 19 | #define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400 |
| 20 | #define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82000 |
| 21 | #define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82400 |
| 22 | #define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D82800 |
| 23 | #define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D82C00 |
| 24 | #define PULSAR_SL_MAIN_0_MEMBDG_RMST0 0x45D84000 |
| 25 | #define PULSAR_SL_MAIN_0_MEMBDG_RMST1 0x45D84400 |
| 26 | #define PULSAR_SL_MAIN_0_MEMBDG_WMST0 0x45D84800 |
| 27 | #define PULSAR_SL_MAIN_0_MEMBDG_WMST1 0x45D84C00 |
| 28 | #define PULSAR_SL_MAIN_1_MEMBDG_RMST0 0x45D85000 |
| 29 | #define PULSAR_SL_MAIN_1_MEMBDG_RMST1 0x45D85400 |
| 30 | #define PULSAR_SL_MAIN_1_MEMBDG_WMST0 0x45D85800 |
| 31 | #define PULSAR_SL_MAIN_1_MEMBDG_WMST1 0x45D85C00 |
| 32 | #define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 |
| 33 | #define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 |
| 34 | #define K3_C66_COREPAC_MAIN_0_C66_CFG 0x45D87000 |
| 35 | #define K3_C66_COREPAC_MAIN_1_C66_CFG 0x45D87400 |
| 36 | #define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D88800 |
| 37 | #define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D89800 |
| 38 | #define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D89C00 |
| 39 | #define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D8A000 |
| 40 | #define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D8A400 |
| 41 | #define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45D8A800 |
| 42 | #define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45D8AC00 |
| 43 | #define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45D8B000 |
| 44 | #define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45D8B400 |
| 45 | #define VPFE_MAIN_0_VBUSM_DMA 0x45D8C000 |
| 46 | #define VPE_MAIN_0_VPDMA_MST0 0x45D8C400 |
| 47 | #define VPE_MAIN_0_VPDMA_MST1 0x45D8C800 |
| 48 | #define PCIE_G4X2_MAIN_0_PCIE_MST_RD_HP 0x45D90000 |
| 49 | #define PCIE_G4X2_MAIN_0_PCIE_MST_RD_LP 0x45D90400 |
| 50 | #define PCIE_G4X2_MAIN_0_PCIE_MST_WR_HP 0x45D90800 |
| 51 | #define PCIE_G4X2_MAIN_0_PCIE_MST_WR_LP 0x45D90C00 |
| 52 | #define PCIE_G4X2_MAIN_1_PCIE_MST_RD_HP 0x45D91000 |
| 53 | #define PCIE_G4X2_MAIN_1_PCIE_MST_RD_LP 0x45D91400 |
| 54 | #define PCIE_G4X2_MAIN_1_PCIE_MST_WR_HP 0x45D91800 |
| 55 | #define PCIE_G4X2_MAIN_1_PCIE_MST_WR_LP 0x45D91C00 |
| 56 | #define PCIE_G4X2_MAIN_2_PCIE_MST_RD_HP 0x45D92000 |
| 57 | #define PCIE_G4X2_MAIN_2_PCIE_MST_RD_LP 0x45D92400 |
| 58 | #define PCIE_G4X2_MAIN_2_PCIE_MST_WR_HP 0x45D92800 |
| 59 | #define PCIE_G4X2_MAIN_2_PCIE_MST_WR_LP 0x45D92C00 |
| 60 | #define PCIE_G4X2_MAIN_3_PCIE_MST_RD_HP 0x45D93000 |
| 61 | #define PCIE_G4X2_MAIN_3_PCIE_MST_RD_LP 0x45D93400 |
| 62 | #define PCIE_G4X2_MAIN_3_PCIE_MST_WR_HP 0x45D93800 |
| 63 | #define PCIE_G4X2_MAIN_3_PCIE_MST_WR_LP 0x45D93C00 |
| 64 | #define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D98000 |
| 65 | #define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D98400 |
| 66 | #define USB3P0SS_16FFC_MAIN_1_MSTR0 0x45D98800 |
| 67 | #define USB3P0SS_16FFC_MAIN_1_MSTW0 0x45D98C00 |
| 68 | #define USB3P0SS_16FFC_MAIN_2_MSTR0 0x45D99000 |
| 69 | #define USB3P0SS_16FFC_MAIN_2_MSTW0 0x45D99400 |
| 70 | #define MLBSS2P0_MAIN_0_MLBSS_DMA_VBUSP 0x45D99C00 |
| 71 | #define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9A000 |
| 72 | #define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9A400 |
| 73 | #define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9B000 |
| 74 | #define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B400 |
| 75 | #define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_RD 0x45D9B800 |
| 76 | #define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_WR 0x45D9BC00 |
| 77 | #define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 |
| 78 | #define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 |
| 79 | #define PULSAR_SL_MAIN_0_CPU0_PMST 0x45DA4000 |
| 80 | #define PULSAR_SL_MAIN_0_CPU1_PMST 0x45DA4400 |
| 81 | #define PULSAR_SL_MAIN_1_CPU0_PMST 0x45DA4800 |
| 82 | #define PULSAR_SL_MAIN_1_CPU1_PMST 0x45DA4C00 |
| 83 | #define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 |
| 84 | #define K3_D5520MP2_MAIN_0_M_VBUSM_R 0x45DC0400 |
| 85 | #define K3_D5520MP2_MAIN_0_M_VBUSM_W 0x45DC0800 |
| 86 | #define K3_VXE384MP2_MAIN_0_M_VBUSM_R 0x45DC0C00 |
| 87 | #define K3_VXE384MP2_MAIN_0_M_VBUSM_W 0x45DC1000 |
| 88 | #define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 |
| 89 | #define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 |
| 90 | #define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 |
| 91 | #define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 |
| 92 | #define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 |
| 93 | #define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_R_ASYNC 0x45DC5000 |
| 94 | #define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_W_ASYNC 0x45DC5800 |
| 95 | #define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_R_ASYNC 0x45DC6000 |
| 96 | #define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_W_ASYNC 0x45DC6800 |