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Andre Przywara47b3cab2017-02-16 01:20:29 +00001/*
2 * Copyright (c) 2016 ARM Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
Jagan Teki053d9a12017-05-25 18:15:36 +000045#include "sun50i-h5.dtsi"
Andre Przywara47b3cab2017-02-16 01:20:29 +000046
Jagan Teki9b646a72017-05-25 18:26:41 +000047#include <dt-bindings/gpio/gpio.h>
48
Andre Przywara47b3cab2017-02-16 01:20:29 +000049/ {
50 model = "OrangePi PC 2";
51 compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
52
Jagan Teki1e8816c2018-05-07 13:03:47 +053053 aliases {
54 serial0 = &uart0;
55 ethernet0 = &emac;
56 };
57
Andre Przywara47b3cab2017-02-16 01:20:29 +000058 chosen {
59 stdout-path = "serial0:115200n8";
60 };
61
62 memory {
63 reg = <0x40000000 0x40000000>;
64 };
65
Andre Przywara47b3cab2017-02-16 01:20:29 +000066 soc {
67 reg_vcc3v3: vcc3v3 {
68 compatible = "regulator-fixed";
69 regulator-name = "vcc3v3";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 };
73 };
74};
75
Jagan Tekiad812222018-05-07 13:03:48 +053076&ehci0 {
77 status = "okay";
78};
79
Jagan Teki1e8816c2018-05-07 13:03:47 +053080&ehci1 {
81 status = "okay";
82};
83
84&emac {
85 pinctrl-names = "default";
86 pinctrl-0 = <&emac_rgmii_pins>;
87 phy-mode = "rgmii";
88 phy-handle = <&ext_rgmii_phy>;
89 status = "okay";
90};
91
92&external_mdio {
93 ext_rgmii_phy: ethernet-phy@1 {
94 compatible = "ethernet-phy-ieee802.3-c22";
95 reg = <1>;
96 };
97};
98
Andre Przywara47b3cab2017-02-16 01:20:29 +000099&mmc0 {
100 compatible = "allwinner,sun50i-h5-mmc",
101 "allwinner,sun50i-a64-mmc",
102 "allwinner,sun5i-a13-mmc";
103 pinctrl-names = "default";
104 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
105 vmmc-supply = <&reg_vcc3v3>;
106 bus-width = <4>;
Jagan Teki9b646a72017-05-25 18:26:41 +0000107 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
Andre Przywara47b3cab2017-02-16 01:20:29 +0000108 cd-inverted;
109 status = "okay";
110};
111
Jagan Tekiad812222018-05-07 13:03:48 +0530112&ohci0 {
113 status = "okay";
114};
115
Andre Przywara47b3cab2017-02-16 01:20:29 +0000116&ohci1 {
117 status = "okay";
118};
119
Jagan Teki1e8816c2018-05-07 13:03:47 +0530120&uart0 {
Andre Przywara47b3cab2017-02-16 01:20:29 +0000121 pinctrl-names = "default";
Jagan Teki1e8816c2018-05-07 13:03:47 +0530122 pinctrl-0 = <&uart0_pins_a>;
Andre Przywara47b3cab2017-02-16 01:20:29 +0000123 status = "okay";
Andre Przywaraeb6b7512018-04-04 01:31:19 +0100124};
Andre Przywara47b3cab2017-02-16 01:20:29 +0000125
Jagan Tekiad812222018-05-07 13:03:48 +0530126&usb_otg {
127 dr_mode = "otg";
128 status = "okay";
129};
130
Jagan Teki1e8816c2018-05-07 13:03:47 +0530131&usbphy {
132 status = "okay";
Andre Przywara47b3cab2017-02-16 01:20:29 +0000133};