| Masahiro Yamada | 3de725b | 2015-12-16 10:54:07 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source commonly used by UniPhier ARM SoCs |
| 3 | * |
| 4 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ X11 |
| 7 | */ |
| 8 | |
| 9 | /include/ "skeleton.dtsi" |
| 10 | |
| 11 | / { |
| 12 | soc: soc { |
| 13 | compatible = "simple-bus"; |
| 14 | #address-cells = <1>; |
| 15 | #size-cells = <1>; |
| 16 | ranges; |
| 17 | interrupt-parent = <&intc>; |
| 18 | |
| 19 | extbus: extbus { |
| 20 | compatible = "simple-bus"; |
| 21 | #address-cells = <2>; |
| 22 | #size-cells = <1>; |
| 23 | }; |
| 24 | |
| 25 | serial0: serial@54006800 { |
| 26 | compatible = "socionext,uniphier-uart"; |
| 27 | status = "disabled"; |
| 28 | reg = <0x54006800 0x40>; |
| 29 | interrupts = <0 33 4>; |
| 30 | pinctrl-names = "default"; |
| 31 | pinctrl-0 = <&pinctrl_uart0>; |
| 32 | clocks = <&uart_clk>; |
| 33 | }; |
| 34 | |
| 35 | serial1: serial@54006900 { |
| 36 | compatible = "socionext,uniphier-uart"; |
| 37 | status = "disabled"; |
| 38 | reg = <0x54006900 0x40>; |
| 39 | interrupts = <0 35 4>; |
| 40 | pinctrl-names = "default"; |
| 41 | pinctrl-0 = <&pinctrl_uart1>; |
| 42 | clocks = <&uart_clk>; |
| 43 | }; |
| 44 | |
| 45 | serial2: serial@54006a00 { |
| 46 | compatible = "socionext,uniphier-uart"; |
| 47 | status = "disabled"; |
| 48 | reg = <0x54006a00 0x40>; |
| 49 | interrupts = <0 37 4>; |
| 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&pinctrl_uart2>; |
| 52 | clocks = <&uart_clk>; |
| 53 | }; |
| 54 | |
| 55 | serial3: serial@54006b00 { |
| 56 | compatible = "socionext,uniphier-uart"; |
| 57 | status = "disabled"; |
| 58 | reg = <0x54006b00 0x40>; |
| 59 | interrupts = <0 177 4>; |
| 60 | pinctrl-names = "default"; |
| 61 | pinctrl-0 = <&pinctrl_uart3>; |
| 62 | clocks = <&uart_clk>; |
| 63 | }; |
| 64 | |
| 65 | system-bus-controller@58c00000 { |
| 66 | compatible = "socionext,uniphier-system-bus-controller"; |
| 67 | reg = <0x58c00000 0x400>, <0x59800000 0x2000>; |
| 68 | }; |
| 69 | |
| 70 | timer@60000200 { |
| 71 | compatible = "arm,cortex-a9-global-timer"; |
| 72 | reg = <0x60000200 0x20>; |
| 73 | interrupts = <1 11 0x104>; |
| 74 | clocks = <&arm_timer_clk>; |
| 75 | }; |
| 76 | |
| 77 | timer@60000600 { |
| 78 | compatible = "arm,cortex-a9-twd-timer"; |
| 79 | reg = <0x60000600 0x20>; |
| 80 | interrupts = <1 13 0x104>; |
| 81 | clocks = <&arm_timer_clk>; |
| 82 | }; |
| 83 | |
| 84 | intc: interrupt-controller@60001000 { |
| 85 | compatible = "arm,cortex-a9-gic"; |
| 86 | reg = <0x60001000 0x1000>, |
| 87 | <0x60000100 0x100>; |
| 88 | #interrupt-cells = <3>; |
| 89 | interrupt-controller; |
| 90 | }; |
| 91 | |
| 92 | pinctrl: pinctrl@5f801000 { |
| 93 | /* specify compatible in each SoC DTSI */ |
| 94 | reg = <0x5f801000 0xe00>; |
| 95 | }; |
| 96 | |
| 97 | nand: nand@68000000 { |
| 98 | compatible = "denali,denali-nand-dt"; |
| 99 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; |
| 100 | reg-names = "nand_data", "denali_reg"; |
| 101 | }; |
| 102 | }; |
| 103 | }; |
| 104 | |
| 105 | /include/ "uniphier-pinctrl.dtsi" |