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Heiko Schocher4e5781b2008-08-21 20:44:49 +02001/*
Heiko Schocher028c79f2009-09-23 07:56:04 +02002 * (C) Copyright 2008-2009
Heiko Schocher4e5781b2008-08-21 20:44:49 +02003 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * (C) Copyright 2003-2005
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4e5781b2008-08-21 20:44:49 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
Heiko Schocher028c79f2009-09-23 07:56:04 +020019#define CONFIG_MUCMC52 1 /* MUCMC52 board */
20#define CONFIG_HOSTNAME mucmc52
Heiko Schocher4e5781b2008-08-21 20:44:49 +020021
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020022#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xFFF00000
24#endif
25
Heiko Schocher028c79f2009-09-23 07:56:04 +020026#include "manroland/common.h"
27#include "manroland/mpc5200-common.h"
Heiko Schocher4e5781b2008-08-21 20:44:49 +020028
29#define CONFIG_LAST_STAGE_INIT
Heiko Schocher4e5781b2008-08-21 20:44:49 +020030/*
31 * Serial console configuration
32 */
Heiko Schocher4e5781b2008-08-21 20:44:49 +020033#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Heiko Schocher4e5781b2008-08-21 20:44:49 +020034
Heiko Schocher4e5781b2008-08-21 20:44:49 +020035#define CONFIG_CMD_PCI
Heiko Schocher4e5781b2008-08-21 20:44:49 +020036
37/*
Heiko Schocher4e5781b2008-08-21 20:44:49 +020038 * Flash configuration
39 */
Heiko Schocher028c79f2009-09-23 07:56:04 +020040#define CONFIG_SYS_MAX_FLASH_SECT 67
Heiko Schocher4e5781b2008-08-21 20:44:49 +020041
42/*
43 * Environment settings
44 */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020045#define CONFIG_ENV_SECT_SIZE 0x20000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020046
47/*
48 * Memory map
49 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_STATUS1_BASE 0x80600200
51#define CONFIG_SYS_STATUS2_BASE 0x80600300
52#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
53#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020054
Heiko Schocher4e5781b2008-08-21 20:44:49 +020055/*
56 * GPIO configuration
57 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
Heiko Schocher4e5781b2008-08-21 20:44:49 +020059
Heiko Schocher028c79f2009-09-23 07:56:04 +020060#define CONFIG_SYS_MEMTEST_START 0x00100000
61#define CONFIG_SYS_MEMTEST_END 0x00f00000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020062
Heiko Schocher028c79f2009-09-23 07:56:04 +020063#define CONFIG_SYS_LOAD_ADDR 0x100000
Heiko Schocher4e5781b2008-08-21 20:44:49 +020064
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
Heiko Schocher4e5781b2008-08-21 20:44:49 +020066
67/* 8Mbit SRAM @0x80100000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_CS1_SIZE 0x00100000
69#define CONFIG_SYS_CS1_CFG 0x00019B00
Heiko Schocher4e5781b2008-08-21 20:44:49 +020070
Heiko Schocherab8e7f32010-09-13 12:12:33 +020071#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
72
Heiko Schocher4e5781b2008-08-21 20:44:49 +020073/* FRAM 32Kbyte @0x80700000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_CS2_START 0x80700000
75#define CONFIG_SYS_CS2_SIZE 0x00008000
76#define CONFIG_SYS_CS2_CFG 0x00019800
Heiko Schocher4e5781b2008-08-21 20:44:49 +020077
78/* Display H1, Status Inputs, EPLD @0x80600000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_CS3_START 0x80600000
80#define CONFIG_SYS_CS3_SIZE 0x00100000
81#define CONFIG_SYS_CS3_CFG 0x00019800
Heiko Schocher4e5781b2008-08-21 20:44:49 +020082
83/* PMI Unicast 32Kbyte @0x80800000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
85#define CONFIG_SYS_CS6_SIZE 0x00008000
86#define CONFIG_SYS_CS6_CFG 0xFFFFF930
Heiko Schocher4e5781b2008-08-21 20:44:49 +020087
88/* PMI Broadcast 32Kbyte @0x80810000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
90#define CONFIG_SYS_CS7_SIZE 0x00008000
91#define CONFIG_SYS_CS7_CFG 0xFF00F930
Heiko Schocher4e5781b2008-08-21 20:44:49 +020092
Heiko Schocher4e5781b2008-08-21 20:44:49 +020093/*-----------------------------------------------------------------------
94 * IDE/ATA stuff Supports IDE harddisk
95 *-----------------------------------------------------------------------
96 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
Heiko Schocher4e5781b2008-08-21 20:44:49 +020098
Heiko Schocher4e5781b2008-08-21 20:44:49 +020099/*
100 * PCI Mapping:
101 * 0x40000000 - 0x4fffffff - PCI Memory
102 * 0x50000000 - 0x50ffffff - PCI IO Space
103 */
104#define CONFIG_PCI 1
105#define CONFIG_PCI_PNP 1
106#define CONFIG_PCI_SCAN_SHOW 1
107#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
108
109#define CONFIG_PCI_MEM_BUS 0x40000000
110#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
111#define CONFIG_PCI_MEM_SIZE 0x10000000
112
113#define CONFIG_PCI_IO_BUS 0x50000000
114#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
115#define CONFIG_PCI_IO_SIZE 0x01000000
116
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200118
119/*---------------------------------------------------------------------*/
120/* Display addresses */
121/*---------------------------------------------------------------------*/
122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
124#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
Heiko Schocher4e5781b2008-08-21 20:44:49 +0200125
126#endif /* __CONFIG_H */