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Michael Schwingen06a9e122008-01-16 19:53:23 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * Configuration settings for the AcTux-4 board.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Michael Schwingen06a9e122008-01-16 19:53:23 +01008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_IXP425 1
14#define CONFIG_ACTUX4 1
15
Marek Vasutf0ed2fb2012-03-06 00:45:35 +010016#define CONFIG_MACH_TYPE 1532
17
Michael Schwingen06a9e122008-01-16 19:53:23 +010018#define CONFIG_DISPLAY_CPUINFO 1
19#define CONFIG_DISPLAY_BOARDINFO 1
20
Jean-Christophe PLAGNIOL-VILLARD08cae4d2009-01-31 09:10:48 +010021#define CONFIG_IXP_SERIAL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
Michael Schwingen06a9e122008-01-16 19:53:23 +010023#define CONFIG_BAUDRATE 115200
24#define CONFIG_BOOTDELAY 3
25#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Michael Schwingen67ea3d92011-05-23 00:00:07 +020026#define CONFIG_BOARD_EARLY_INIT_F 1
Michael Schwingen06a9e122008-01-16 19:53:23 +010027
28/***************************************************************
29 * U-boot generic defines start here.
30 ***************************************************************/
Michael Schwingen06a9e122008-01-16 19:53:23 +010031/* Size of malloc() pool */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Michael Schwingen06a9e122008-01-16 19:53:23 +010033
34/* allow to overwrite serial and ethaddr */
35#define CONFIG_ENV_OVERWRITE
36
37/* Command line configuration */
38#include <config_cmd_default.h>
39
40#define CONFIG_CMD_ELF
41
Michael Schwingen67ea3d92011-05-23 00:00:07 +020042#define CONFIG_PCI
43#ifdef CONFIG_PCI
44#define CONFIG_CMD_PCI
45#define CONFIG_PCI_PNP
46#define CONFIG_IXP_PCI
47#define CONFIG_PCI_SCAN_SHOW
48#define CONFIG_CMD_PCI_ENUM
49#endif
50
Michael Schwingen06a9e122008-01-16 19:53:23 +010051#define CONFIG_BOOTCOMMAND "run boot_flash"
52/* enable passing of ATAGs */
53#define CONFIG_CMDLINE_TAG 1
54#define CONFIG_SETUP_MEMORY_TAGS 1
55#define CONFIG_INITRD_TAG 1
56
57#if defined(CONFIG_CMD_KGDB)
58# define CONFIG_KGDB_BAUDRATE 230400
59/* which serial port to use */
60# define CONFIG_KGDB_SER_INDEX 1
61#endif
62
63/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_LONGHELP
65#define CONFIG_SYS_PROMPT "=> "
Michael Schwingen06a9e122008-01-16 19:53:23 +010066/* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_CBSIZE 256
Michael Schwingen06a9e122008-01-16 19:53:23 +010068/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Michael Schwingen06a9e122008-01-16 19:53:23 +010070/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#define CONFIG_SYS_MAXARGS 16
Michael Schwingen06a9e122008-01-16 19:53:23 +010072/* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Michael Schwingen06a9e122008-01-16 19:53:23 +010074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_MEMTEST_START 0x00400000
76#define CONFIG_SYS_MEMTEST_END 0x00800000
Michael Schwingen06a9e122008-01-16 19:53:23 +010077
Michael Schwingen67ea3d92011-05-23 00:00:07 +020078/* timer clock - 2* OSC_IN system clock */
79#define CONFIG_IXP425_TIMER_CLK 66000000
80#define CONFIG_SYS_HZ 1000
Michael Schwingen06a9e122008-01-16 19:53:23 +010081
82/* default load address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_LOAD_ADDR 0x00010000
Michael Schwingen06a9e122008-01-16 19:53:23 +010084
85/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
Michael Schwingen06a9e122008-01-16 19:53:23 +010087 115200, 230400 }
88#define CONFIG_SERIAL_RTS_ACTIVE 1
89
Michael Schwingen06a9e122008-01-16 19:53:23 +010090/* Expansion bus settings */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_EXP_CS0 0xbd113003
Michael Schwingen06a9e122008-01-16 19:53:23 +010092
93/* SDRAM settings */
94#define CONFIG_NR_DRAM_BANKS 1
95#define PHYS_SDRAM_1 0x00000000
Michael Schwingen67ea3d92011-05-23 00:00:07 +020096#define CONFIG_SYS_SDRAM_BASE 0x00000000
Michael Schwingen06a9e122008-01-16 19:53:23 +010097
98/* 32MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_SDR_CONFIG 0x18
Michael Schwingen06a9e122008-01-16 19:53:23 +0100100#define PHYS_SDRAM_1_SIZE 0x02000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
102#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
103#define CONFIG_SYS_DRAM_SIZE 0x02000000
Michael Schwingen06a9e122008-01-16 19:53:23 +0100104
105/* FLASH organization */
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200106#define CONFIG_SYS_TEXT_BASE 0x50000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_MAX_FLASH_BANKS 2
Michael Schwingen06a9e122008-01-16 19:53:23 +0100108/* max # of sectors per chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_SYS_MAX_FLASH_SECT 70
Michael Schwingen06a9e122008-01-16 19:53:23 +0100110#define PHYS_FLASH_1 0x50000000
111#define PHYS_FLASH_2 0x51000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
Michael Schwingen06a9e122008-01-16 19:53:23 +0100113
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
115#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
116#define CONFIG_SYS_MONITOR_LEN (252 << 10)
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200117#define CONFIG_BOARD_SIZE_LIMIT 258048
Michael Schwingen06a9e122008-01-16 19:53:23 +0100118
119/* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200121#define CONFIG_FLASH_CFI_DRIVER
Michael Schwingen06a9e122008-01-16 19:53:23 +0100122/* board provides its own flash_init code */
123#define CONFIG_FLASH_CFI_LEGACY 1
124/* no byte writes on IXP4xx */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Michael Schwingen06a9e122008-01-16 19:53:23 +0100126/* SST 39VF020 etc. support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1
Michael Schwingen06a9e122008-01-16 19:53:23 +0100128
129/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_EMPTY_INFO
Michael Schwingen06a9e122008-01-16 19:53:23 +0100131
132/* Ethernet */
133
134/* include IXP4xx NPE support */
135#define CONFIG_IXP4XX_NPE 1
Michael Schwingen06a9e122008-01-16 19:53:23 +0100136
Michael Schwingen06a9e122008-01-16 19:53:23 +0100137/* NPE0 PHY address */
138#define CONFIG_PHY_ADDR 0x1C
139/* MII PHY management */
140#define CONFIG_MII 1
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200141
Michael Schwingen06a9e122008-01-16 19:53:23 +0100142/* Number of ethernet rx buffers & descriptors */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_RX_ETH_BUFFER 16
Michael Schwingen06a9e122008-01-16 19:53:23 +0100144
145#define CONFIG_CMD_DHCP
146#define CONFIG_CMD_NET
147#define CONFIG_CMD_MII
148#define CONFIG_CMD_PING
149#undef CONFIG_CMD_NFS
150
151/* BOOTP options */
152#define CONFIG_BOOTP_BOOTFILESIZE
153#define CONFIG_BOOTP_BOOTPATH
154#define CONFIG_BOOTP_GATEWAY
155#define CONFIG_BOOTP_HOSTNAME
156
157/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_CACHELINE_SIZE 32
Michael Schwingen06a9e122008-01-16 19:53:23 +0100159
160/* environment organization: one complete 4k flash sector */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200161#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200162#define CONFIG_ENV_SIZE 0x1000
163#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000)
Michael Schwingen06a9e122008-01-16 19:53:23 +0100164
165#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARD1948d6c2009-01-31 09:53:39 +0100166 "npe_ucode=51000000\0" \
Michael Schwingen06a9e122008-01-16 19:53:23 +0100167 "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \
168 "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \
169 "kerneladdr=51020000\0" \
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200170 "kernelfile=actux4/uImage\0" \
171 "rootfile=actux4/rootfs\0" \
Michael Schwingen06a9e122008-01-16 19:53:23 +0100172 "rootaddr=51160000\0" \
173 "loadaddr=10000\0" \
174 "updateboot_ser=mw.b 10000 ff 40000;" \
175 " loady ${loadaddr};" \
176 " run eraseboot writeboot\0" \
177 "updateboot_net=mw.b 10000 ff 40000;" \
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200178 " tftp ${loadaddr} actux4/u-boot.bin;" \
Michael Schwingen06a9e122008-01-16 19:53:23 +0100179 " run eraseboot writeboot\0" \
180 "eraseboot=protect off 50000000 5003efff;" \
181 " erase 50000000 +${filesize}\0" \
182 "writeboot=cp.b 10000 50000000 ${filesize}\0" \
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200183 "updateucode=loady;" \
184 " era ${npe_ucode} +${filesize};" \
185 " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
Michael Schwingen06a9e122008-01-16 19:53:23 +0100186 "updateroot=tftp ${loadaddr} ${rootfile};" \
187 " era ${rootaddr} +${filesize};" \
188 " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
189 "updatekern=tftp ${loadaddr} ${kernelfile};" \
190 " era ${kerneladdr} +${filesize};" \
191 " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
192 "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
193 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
194 "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
195 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
196 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
197 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
198 "boot_flash=run flashargs addtty addeth;" \
199 " bootm ${kerneladdr}\0" \
200 "boot_net=run netargs addtty addeth;" \
201 " tftpboot ${loadaddr} ${kernelfile};" \
202 " bootm\0"
203
Michael Schwingen67ea3d92011-05-23 00:00:07 +0200204/* additions for new relocation code, must be added to all boards */
205#define CONFIG_SYS_INIT_SP_ADDR \
206 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
207
Michael Schwingen06a9e122008-01-16 19:53:23 +0100208#endif /* __CONFIG_H */