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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babiccacdd2b2010-04-18 19:27:44 +02002/*
3 * (C) Copyright 2010
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
Stefano Babiccacdd2b2010-04-18 19:27:44 +02007 */
8
9
10#ifndef __MC13892_H__
11#define __MC13892_H__
12
13/* REG_CHARGE */
14
Shawn Guo4546eb72010-10-27 23:36:04 +080015#define VCHRG0 (1 << 0)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020016#define VCHRG1 (1 << 1)
17#define VCHRG2 (1 << 2)
18#define ICHRG0 (1 << 3)
19#define ICHRG1 (1 << 4)
20#define ICHRG2 (1 << 5)
21#define ICHRG3 (1 << 6)
Shawn Guo4546eb72010-10-27 23:36:04 +080022#define TREN (1 << 7)
23#define ACKLPB (1 << 8)
24#define THCHKB (1 << 9)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020025#define FETOVRD (1 << 10)
26#define FETCTRL (1 << 11)
27#define RVRSMODE (1 << 13)
Shawn Guo4546eb72010-10-27 23:36:04 +080028#define PLIM0 (1 << 15)
29#define PLIM1 (1 << 16)
30#define PLIMDIS (1 << 17)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020031#define CHRGLEDEN (1 << 18)
Shawn Guo4546eb72010-10-27 23:36:04 +080032#define CHGTMRRST (1 << 19)
Stefano Babiccacdd2b2010-04-18 19:27:44 +020033#define CHGRESTART (1 << 20)
34#define CHGAUTOB (1 << 21)
35#define CYCLB (1 << 22)
36#define CHGAUTOVIB (1 << 23)
37
38/* REG_SETTING_0/1 */
39#define VO_1_20V 0
40#define VO_1_30V 1
41#define VO_1_50V 2
42#define VO_1_80V 3
43#define VO_1_10V 4
44#define VO_2_00V 5
45#define VO_2_77V 6
46#define VO_2_40V 7
47
48#define VIOL 2
49#define VDIG 4
50#define VGEN 6
51
52/* SWxMode for Normal/Standby Mode */
53#define SWMODE_OFF_OFF 0
54#define SWMODE_PWM_OFF 1
55#define SWMODE_PWMPS_OFF 2
56#define SWMODE_PFM_OFF 3
57#define SWMODE_AUTO_OFF 4
58#define SWMODE_PWM_PWM 5
59#define SWMODE_PWM_AUTO 6
60#define SWMODE_AUTO_AUTO 8
61#define SWMODE_PWM_PWMPS 9
62#define SWMODE_PWMS_PWMPS 10
63#define SWMODE_PWMS_AUTO 11
64#define SWMODE_AUTO_PFM 12
65#define SWMODE_PWM_PFM 13
66#define SWMODE_PWMS_PFM 14
67#define SWMODE_PFM_PFM 15
68#define SWMODE_MASK 0x0F
69
70#define SWMODE1_SHIFT 0
71#define SWMODE2_SHIFT 10
72#define SWMODE3_SHIFT 0
73#define SWMODE4_SHIFT 8
74
75/* Fields in REG_SETTING_1 */
76#define VVIDEO_2_7 (0 << 2)
77#define VVIDEO_2_775 (1 << 2)
78#define VVIDEO_2_5 (2 << 2)
79#define VVIDEO_2_6 (3 << 2)
80#define VVIDEO_MASK (3 << 2)
81#define VAUDIO_2_3 (0 << 4)
82#define VAUDIO_2_5 (1 << 4)
83#define VAUDIO_2_775 (2 << 4)
84#define VAUDIO_3_0 (3 << 4)
85#define VAUDIO_MASK (3 << 4)
86#define VSD_1_8 (0 << 6)
87#define VSD_2_0 (1 << 6)
88#define VSD_2_6 (2 << 6)
89#define VSD_2_7 (3 << 6)
90#define VSD_2_8 (4 << 6)
91#define VSD_2_9 (5 << 6)
92#define VSD_3_0 (6 << 6)
93#define VSD_3_15 (7 << 6)
94#define VSD_MASK (7 << 6)
95#define VGEN1_1_2 0
96#define VGEN1_1_5 1
97#define VGEN1_2_775 2
98#define VGEN1_3_15 3
99#define VGEN1_MASK 3
100#define VGEN2_1_2 (0 << 6)
101#define VGEN2_1_5 (1 << 6)
102#define VGEN2_1_6 (2 << 6)
103#define VGEN2_1_8 (3 << 6)
104#define VGEN2_2_7 (4 << 6)
105#define VGEN2_2_8 (5 << 6)
106#define VGEN2_3_0 (6 << 6)
107#define VGEN2_3_15 (7 << 6)
108#define VGEN2_MASK (7 << 6)
109
110/* Fields in REG_SETTING_1 */
111#define VGEN3_1_8 (0 << 14)
112#define VGEN3_2_9 (1 << 14)
113#define VGEN3_MASK (1 << 14)
114#define VDIG_1_05 (0 << 4)
115#define VDIG_1_25 (1 << 4)
116#define VDIG_1_65 (2 << 4)
117#define VDIG_1_8 (3 << 4)
118#define VDIG_MASK (3 << 4)
119#define VCAM_2_5 (0 << 16)
120#define VCAM_2_6 (1 << 16)
121#define VCAM_2_75 (2 << 16)
122#define VCAM_3_0 (3 << 16)
123#define VCAM_MASK (3 << 16)
124
Marek Vasut030808f2011-09-28 02:07:26 +0000125/* Reg Mode 0 */
126#define VGEN1EN (1 << 0)
127#define VGEN1STBY (1 << 1)
128#define VGEN1MODE (1 << 2)
129#define VIOHIEN (1 << 3)
130#define VIOHISTBY (1 << 4)
131#define VDIGEN (1 << 9)
132#define VDIGSTBY (1 << 10)
133#define VGEN2EN (1 << 12)
134#define VGEN2STBY (1 << 13)
135#define VGEN2MODE (1 << 14)
136#define VPLLEN (1 << 15)
137#define VPLLSTBY (1 << 16)
138#define VUSBEN (1 << 18)
139#define VUSBSTBY (1 << 19)
140
Stefano Babiccacdd2b2010-04-18 19:27:44 +0200141/* Reg Mode 1 */
142#define VGEN3EN (1 << 0)
143#define VGEN3STBY (1 << 1)
144#define VGEN3MODE (1 << 2)
145#define VGEN3CONFIG (1 << 3)
146#define VCAMEN (1 << 6)
147#define VCAMSTBY (1 << 7)
148#define VCAMMODE (1 << 8)
149#define VCAMCONFIG (1 << 9)
150#define VVIDEOEN (1 << 12)
151#define VIDEOSTBY (1 << 13)
152#define VVIDEOMODE (1 << 14)
153#define VAUDIOEN (1 << 15)
154#define VAUDIOSTBY (1 << 16)
155#define VSDEN (1 << 18)
156#define VSDSTBY (1 << 19)
157#define VSDMODE (1 << 20)
158
Stefano Babice1b6f592010-07-06 19:32:09 +0200159/* Reg Power Control 2*/
160#define WDIRESET (1 << 12)
161
Liu Hui-R643434cf4cd72011-01-03 22:27:42 +0000162/* SWx Output Volts */
163#define SWX_OUT_MASK 0x1F
164#define SWX_OUT_1_25 0x1A
165#define SWX_OUT_1_30 0X1C
166
Marek Vasut00f3a222011-01-19 04:40:35 +0000167/* Buck Switchers (SW1,2,3,4) Output Voltage */
168/*
169 * NOTE: These values are for SWxHI = 0,
170 * SWxHI = 1 adds 0.5V to the desired voltage
171 */
172#define SWx_0_600V 0
173#define SWx_0_625V 1
174#define SWx_0_650V 2
175#define SWx_0_675V 3
176#define SWx_0_700V 4
177#define SWx_0_725V 5
178#define SWx_0_750V 6
179#define SWx_0_775V 7
180#define SWx_0_800V 8
181#define SWx_0_825V 9
182#define SWx_0_850V 10
183#define SWx_0_875V 11
184#define SWx_0_900V 12
185#define SWx_0_925V 13
186#define SWx_0_950V 14
187#define SWx_0_975V 15
188#define SWx_1_000V 16
189#define SWx_1_025V 17
190#define SWx_1_050V 18
191#define SWx_1_075V 19
192#define SWx_1_100V 20
193#define SWx_1_125V 21
194#define SWx_1_150V 22
195#define SWx_1_175V 23
196#define SWx_1_200V 24
197#define SWx_1_225V 25
198#define SWx_1_250V 26
199#define SWx_1_275V 27
200#define SWx_1_300V 28
201#define SWx_1_325V 29
202#define SWx_1_350V 30
203#define SWx_1_375V 31
204#define SWx_VOLT_MASK 0x1F
205
Stefano Babiccacdd2b2010-04-18 19:27:44 +0200206#endif