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git01.mediatek.com / filogic / uboot / 1681ca024e9ba41cad76b507c9547477908cc6f2 / . / test / dm / misc.c
blob: 8bdd8c64bca2bd411efac6148b2f37aa7caec7d4 [file] [log] [blame]
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 */
6
Tom Riniabb9a042024-05-18 20:20:43 -0600[diff] [blame]7#include <common.h>
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]8#include <dm.h>
9#include <dm/test.h>
10#include <misc.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]11#include <test/test.h>
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]12#include <test/ut.h>
13
14static int dm_test_misc(struct unit_test_state *uts)
15{
16 struct udevice *dev;
17 u8 buf[16];
18 int id;
19 ulong last_ioctl;
20 bool enabled;
21
22 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "misc-test", &dev));
23
24 /* Read / write tests */
Simon Glass587dc402018-11-06 15:21:39 -0700[diff] [blame]25 ut_asserteq(4, misc_write(dev, 0, "TEST", 4));
26 ut_asserteq(5, misc_write(dev, 4, "WRITE", 5));
27 ut_asserteq(9, misc_read(dev, 0, buf, 9));
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]28
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]29 ut_asserteq_mem(buf, "TESTWRITE", 9);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]30
31 /* Call tests */
32
33 id = 0;
34 ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]35 ut_asserteq_mem(buf, "Zero", 4);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]36
37 id = 2;
38 ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]39 ut_asserteq_mem(buf, "Two", 3);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]40
41 ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]42 ut_asserteq_mem(buf, "Forty-two", 9);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]43
44 id = 1;
45 ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]46 ut_asserteq_mem(buf, "Forty-one", 9);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]47
48 /* IOCTL tests */
49
50 ut_assertok(misc_ioctl(dev, 6, NULL));
51 /* Read back last issued ioctl */
52 ut_assertok(misc_call(dev, 2, NULL, 0, &last_ioctl,
53 sizeof(last_ioctl)));
Marek Vasut1531c4e2023-03-10 04:33:13 +0100[diff] [blame]54 ut_asserteq(6, last_ioctl);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]55
56 ut_assertok(misc_ioctl(dev, 23, NULL));
57 /* Read back last issued ioctl */
58 ut_assertok(misc_call(dev, 2, NULL, 0, &last_ioctl,
59 sizeof(last_ioctl)));
Marek Vasut1531c4e2023-03-10 04:33:13 +0100[diff] [blame]60 ut_asserteq(23, last_ioctl);
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]61
62 /* Enable / disable tests */
63
64 /* Read back enable/disable status */
65 ut_assertok(misc_call(dev, 3, NULL, 0, &enabled,
66 sizeof(enabled)));
67 ut_asserteq(true, enabled);
68
69 ut_assertok(misc_set_enabled(dev, false));
70 /* Read back enable/disable status */
71 ut_assertok(misc_call(dev, 3, NULL, 0, &enabled,
72 sizeof(enabled)));
73 ut_asserteq(false, enabled);
74
75 ut_assertok(misc_set_enabled(dev, true));
76 /* Read back enable/disable status */
77 ut_assertok(misc_call(dev, 3, NULL, 0, &enabled,
78 sizeof(enabled)));
79 ut_asserteq(true, enabled);
80
81 return 0;
82}
83
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]84DM_TEST(dm_test_misc, UT_TESTF_SCAN_FDT);