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git01.mediatek.com / filogic / uboot / 1681ca024e9ba41cad76b507c9547477908cc6f2 / . / drivers / video / himax-hx8394.c
blob: 63637b4db0223974ed06ef14bbb84fe16e1f9ba6 [file] [log] [blame]
Ondrej Jirman55453d42023-05-25 14:34:35 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 Ondrej Jirman <megi@xff.cz>
4 */
Tom Riniabb9a042024-05-18 20:20:43 -0600[diff] [blame]5#include <common.h>
Ondrej Jirman55453d42023-05-25 14:34:35 +0200[diff] [blame]6#include <backlight.h>
7#include <dm.h>
8#include <mipi_dsi.h>
9#include <panel.h>
10#include <asm/gpio.h>
11#include <dm/device_compat.h>
12#include <linux/delay.h>
13#include <power/regulator.h>
14
15struct hx8394_panel_priv {
16 struct udevice *reg_vcc;
17 struct udevice *reg_iovcc;
18 struct gpio_desc reset;
19 struct udevice *backlight;
20};
21
22static const struct display_timing default_timing = {
23 .pixelclock.typ = 74250000,
24 .hactive.typ = 720,
25 .hfront_porch.typ = 40,
26 .hback_porch.typ = 40,
27 .hsync_len.typ = 46,
28 .vactive.typ = 1440,
29 .vfront_porch.typ = 7,
30 .vback_porch.typ = 9,
31 .vsync_len.typ = 7,
32 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
33};
34
35#define dsi_dcs_write_seq(device, seq...) do { \
36 static const u8 d[] = { seq }; \
37 int ret; \
38 ret = mipi_dsi_dcs_write_buffer(device, d, ARRAY_SIZE(d)); \
39 if (ret < 0) \
40 return ret; \
41 } while (0)
42
43static int hx8394_init_sequence(struct udevice *dev)
44{
45 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
46 struct mipi_dsi_device *device = plat->device;
47 int ret;
48
49 dsi_dcs_write_seq(device, 0xb9, 0xff, 0x83, 0x94);
50 dsi_dcs_write_seq(device, 0xb1, 0x48, 0x11, 0x71, 0x09, 0x32, 0x24,
51 0x71, 0x31, 0x55, 0x30);
52 dsi_dcs_write_seq(device, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
53 dsi_dcs_write_seq(device, 0xb2, 0x00, 0x80, 0x78, 0x0c, 0x07);
54 dsi_dcs_write_seq(device, 0xb4, 0x12, 0x63, 0x12, 0x63, 0x12, 0x63,
55 0x01, 0x0c, 0x7c, 0x55, 0x00, 0x3f, 0x12, 0x6b, 0x12,
56 0x6b, 0x12, 0x6b, 0x01, 0x0c, 0x7c);
57 dsi_dcs_write_seq(device, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c,
58 0x00, 0x00, 0x32, 0x10, 0x09, 0x00, 0x09, 0x32, 0x15,
59 0xad, 0x05, 0xad, 0x32, 0x00, 0x00, 0x00, 0x00, 0x37,
60 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 0x00, 0x0c, 0x40);
61 dsi_dcs_write_seq(device, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b,
62 0x1a, 0x1a, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
63 0x07, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
64 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18,
65 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
66 0x18, 0x18);
67 dsi_dcs_write_seq(device, 0xd6, 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b,
68 0x1a, 0x1a, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
69 0x00, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
70 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x18,
71 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
72 0x18, 0x18);
73 dsi_dcs_write_seq(device, 0xe0, 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18,
74 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b,
75 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49,
76 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 0x04, 0x0c, 0x11,
77 0x13, 0x17, 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54,
78 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a,
79 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f);
80 dsi_dcs_write_seq(device, 0xcc, 0x0b);
81 dsi_dcs_write_seq(device, 0xc0, 0x1f, 0x31);
82 dsi_dcs_write_seq(device, 0xb6, 0x7d, 0x7d);
83 dsi_dcs_write_seq(device, 0xd4, 0x02);
84 dsi_dcs_write_seq(device, 0xbd, 0x01);
85 dsi_dcs_write_seq(device, 0xb1, 0x00);
86 dsi_dcs_write_seq(device, 0xbd, 0x00);
87 dsi_dcs_write_seq(device, 0xc6, 0xed);
88
89 ret = mipi_dsi_dcs_exit_sleep_mode(device);
90 if (ret)
91 return ret;
92
93 /* Panel is operational 120 msec after reset */
94 mdelay(120);
95
96 ret = mipi_dsi_dcs_set_display_on(device);
97 if (ret)
98 return ret;
99
100 return 0;
101}
102
103static int hx8394_panel_enable_backlight(struct udevice *dev)
104{
105 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
106 struct mipi_dsi_device *device = plat->device;
107 struct hx8394_panel_priv *priv = dev_get_priv(dev);
108 int ret;
109
110 ret = mipi_dsi_attach(device);
111 if (ret < 0) {
112 printf("mipi_dsi_attach failed %d\n", ret);
113 return ret;
114 }
115
116 ret = hx8394_init_sequence(dev);
117 if (ret) {
118 printf("hx8394_init_sequence failed %d\n", ret);
119 return ret;
120 }
121
122 if (priv->backlight) {
123 ret = backlight_enable(priv->backlight);
124 if (ret) {
125 printf("backlight enabled failed %d\n", ret);
126 return ret;
127 }
128
129 backlight_set_brightness(priv->backlight, 60);
130 }
131
132 mdelay(10);
133
134 return 0;
135}
136
137static int hx8394_panel_get_display_timing(struct udevice *dev,
138 struct display_timing *timings)
139{
140 memcpy(timings, &default_timing, sizeof(*timings));
141
142 return 0;
143}
144
145static int hx8394_panel_of_to_plat(struct udevice *dev)
146{
147 struct hx8394_panel_priv *priv = dev_get_priv(dev);
148 int ret;
149
150 if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
151 ret = device_get_supply_regulator(dev, "vcc-supply",
152 &priv->reg_vcc);
153 if (ret && ret != -ENOENT) {
154 dev_err(dev, "Warning: cannot get vcc supply\n");
155 return ret;
156 }
157
158 ret = device_get_supply_regulator(dev, "iovcc-supply",
159 &priv->reg_iovcc);
160 if (ret && ret != -ENOENT) {
161 dev_err(dev, "Warning: cannot get iovcc supply\n");
162 return ret;
163 }
164 }
165
166 ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
167 "backlight", &priv->backlight);
168 if (ret)
169 dev_warn(dev, "failed to get backlight\n");
170
171 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
172 GPIOD_IS_OUT);
173 if (ret) {
174 dev_err(dev, "warning: cannot get reset GPIO (%d)\n", ret);
175 if (ret != -ENOENT)
176 return ret;
177 }
178
179 return 0;
180}
181
182static int hx8394_panel_probe(struct udevice *dev)
183{
184 struct hx8394_panel_priv *priv = dev_get_priv(dev);
185 struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
186 int ret;
187
188 dm_gpio_set_value(&priv->reset, true);
189
190 if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
191 dev_dbg(dev, "enable vcc '%s'\n", priv->reg_vcc->name);
192 ret = regulator_set_enable(priv->reg_vcc, true);
193 if (ret)
194 return ret;
195
196 dev_dbg(dev, "enable iovcc '%s'\n", priv->reg_iovcc->name);
197 ret = regulator_set_enable(priv->reg_iovcc, true);
198 if (ret) {
199 regulator_set_enable(priv->reg_vcc, false);
200 return ret;
201 }
202 }
203
204 mdelay(5);
205 dm_gpio_set_value(&priv->reset, false);
206
207 mdelay(180);
208
209 /* fill characteristics of DSI data link */
210 plat->lanes = 4;
211 plat->format = MIPI_DSI_FMT_RGB888;
212 plat->mode_flags = MIPI_DSI_MODE_VIDEO |
213 MIPI_DSI_MODE_VIDEO_BURST;
214
215 return 0;
216}
217
218static const struct panel_ops hx8394_panel_ops = {
219 .enable_backlight = hx8394_panel_enable_backlight,
220 .get_display_timing = hx8394_panel_get_display_timing,
221};
222
223static const struct udevice_id hx8394_panel_ids[] = {
224 { .compatible = "hannstar,hsd060bhw4" },
225 { }
226};
227
228U_BOOT_DRIVER(hx8394_panel) = {
229 .name = "hx8394_panel",
230 .id = UCLASS_PANEL,
231 .of_match = hx8394_panel_ids,
232 .ops = &hx8394_panel_ops,
233 .of_to_plat = hx8394_panel_of_to_plat,
234 .probe = hx8394_panel_probe,
235 .plat_auto = sizeof(struct mipi_dsi_panel_plat),
236 .priv_auto = sizeof(struct hx8394_panel_priv),
237};