Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Xilinx AXI I2C driver |
| 4 | * |
| 5 | * Copyright (C) 2018 Marek Vasut <marex@denx.de> |
| 6 | * |
| 7 | * Based on Linux 4.14.y i2c-xiic.c |
| 8 | * Copyright (c) 2002-2007 Xilinx Inc. |
| 9 | * Copyright (c) 2009-2010 Intel Corporation |
| 10 | */ |
| 11 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 12 | #include <common.h> |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 13 | #include <clk.h> |
| 14 | #include <dm.h> |
| 15 | #include <i2c.h> |
| 16 | #include <wait_bit.h> |
| 17 | #include <asm/io.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 18 | #include <dm/device_compat.h> |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 19 | |
| 20 | struct xilinx_xiic_priv { |
| 21 | void __iomem *base; |
| 22 | struct clk clk; |
| 23 | }; |
| 24 | |
| 25 | #define XIIC_MSB_OFFSET 0 |
| 26 | #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) |
| 27 | |
| 28 | /* |
| 29 | * Register offsets in bytes from RegisterBase. Three is added to the |
| 30 | * base offset to access LSB (IBM style) of the word |
| 31 | */ |
| 32 | #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ |
| 33 | #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ |
| 34 | #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ |
| 35 | #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ |
| 36 | #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ |
| 37 | #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ |
| 38 | #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ |
| 39 | #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ |
| 40 | #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ |
| 41 | #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ |
| 42 | |
| 43 | /* Control Register masks */ |
| 44 | #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ |
| 45 | #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ |
| 46 | #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ |
| 47 | #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ |
| 48 | #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ |
| 49 | #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ |
| 50 | #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ |
| 51 | |
| 52 | /* Status Register masks */ |
| 53 | #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ |
| 54 | #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ |
| 55 | #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ |
| 56 | #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ |
| 57 | #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ |
| 58 | #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ |
| 59 | #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ |
| 60 | #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ |
| 61 | |
| 62 | /* Interrupt Status Register masks Interrupt occurs when... */ |
| 63 | #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ |
| 64 | #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ |
| 65 | #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ |
| 66 | #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ |
| 67 | #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ |
| 68 | #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ |
| 69 | #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ |
| 70 | #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ |
| 71 | |
| 72 | /* The following constants specify the depth of the FIFOs */ |
| 73 | #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ |
| 74 | #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ |
| 75 | |
| 76 | /* |
| 77 | * Tx Fifo upper bit masks. |
| 78 | */ |
| 79 | #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ |
| 80 | #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ |
| 81 | |
| 82 | /* |
| 83 | * The following constants define the register offsets for the Interrupt |
| 84 | * registers. There are some holes in the memory map for reserved addresses |
| 85 | * to allow other registers to be added and still match the memory map of the |
| 86 | * interrupt controller registers |
| 87 | */ |
| 88 | #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ |
| 89 | #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ |
| 90 | #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ |
| 91 | #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ |
| 92 | |
| 93 | #define XIIC_RESET_MASK 0xAUL |
| 94 | |
| 95 | static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags) |
| 96 | { |
| 97 | return (addr << 1) | (flags & I2C_M_RD ? 1 : 0); |
| 98 | } |
| 99 | |
| 100 | static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask) |
| 101 | { |
| 102 | u32 isr = readl(priv->base + XIIC_IISR_OFFSET); |
| 103 | |
| 104 | writel(isr & mask, priv->base + XIIC_IISR_OFFSET); |
| 105 | } |
| 106 | |
| 107 | static int xiic_read_rx(struct xilinx_xiic_priv *priv, |
| 108 | struct i2c_msg *msg, int nmsgs) |
| 109 | { |
| 110 | u8 bytes_in_fifo; |
| 111 | u32 pos = 0; |
| 112 | int i, ret; |
| 113 | |
| 114 | while (pos < msg->len) { |
| 115 | ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, |
| 116 | XIIC_SR_RX_FIFO_EMPTY_MASK, false, |
| 117 | 1000, true); |
| 118 | if (ret) |
| 119 | return ret; |
| 120 | |
| 121 | bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1; |
| 122 | |
| 123 | if (bytes_in_fifo > msg->len) |
| 124 | bytes_in_fifo = msg->len; |
| 125 | |
| 126 | for (i = 0; i < bytes_in_fifo; i++) { |
| 127 | msg->buf[pos++] = readb(priv->base + |
| 128 | XIIC_DRR_REG_OFFSET); |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | |
| 135 | static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv) |
| 136 | { |
| 137 | /* return the actual space left in the FIFO */ |
| 138 | return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1; |
| 139 | } |
| 140 | |
| 141 | static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv, |
| 142 | struct i2c_msg *msg, int nmsgs) |
| 143 | { |
| 144 | u8 fifo_space = xiic_tx_fifo_space(priv); |
| 145 | int len = msg->len; |
| 146 | u32 pos = 0; |
| 147 | |
| 148 | len = (len > fifo_space) ? fifo_space : len; |
| 149 | |
| 150 | while (len--) { |
| 151 | u16 data = msg->buf[pos++]; |
| 152 | |
Melin Tomas | d133b1e | 2019-06-28 12:08:31 +0000 | [diff] [blame] | 153 | if ((msg->len - pos == 0) && nmsgs == 1) { |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 154 | /* last message in transfer -> STOP */ |
| 155 | data |= XIIC_TX_DYN_STOP_MASK; |
| 156 | } |
| 157 | writew(data, priv->base + XIIC_DTR_REG_OFFSET); |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr, |
| 162 | u16 flags, u32 len, u32 nmsgs) |
| 163 | { |
| 164 | struct xilinx_xiic_priv *priv = dev_get_priv(dev); |
| 165 | |
| 166 | xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK); |
| 167 | |
| 168 | if (!(flags & I2C_M_NOSTART)) { |
| 169 | /* write the address */ |
| 170 | u16 data = i2c_8bit_addr_from_flags(addr, flags) | |
| 171 | XIIC_TX_DYN_START_MASK; |
| 172 | if (nmsgs == 1 && len == 0) |
| 173 | /* no data and last message -> add STOP */ |
| 174 | data |= XIIC_TX_DYN_STOP_MASK; |
| 175 | |
| 176 | writew(data, priv->base + XIIC_DTR_REG_OFFSET); |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg, |
| 181 | u32 nmsgs) |
| 182 | { |
| 183 | struct xilinx_xiic_priv *priv = dev_get_priv(dev); |
| 184 | u8 rx_watermark; |
| 185 | |
| 186 | /* Clear and enable Rx full interrupt. */ |
| 187 | xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); |
| 188 | |
| 189 | /* we want to get all but last byte, because the TX_ERROR IRQ is used |
| 190 | * to inidicate error ACK on the address, and negative ack on the last |
| 191 | * received byte, so to not mix them receive all but last. |
| 192 | * In the case where there is only one byte to receive |
| 193 | * we can check if ERROR and RX full is set at the same time |
| 194 | */ |
| 195 | rx_watermark = msg->len; |
| 196 | if (rx_watermark > IIC_RX_FIFO_DEPTH) |
| 197 | rx_watermark = IIC_RX_FIFO_DEPTH; |
| 198 | |
| 199 | writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET); |
| 200 | |
| 201 | xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs); |
| 202 | |
| 203 | xiic_irq_clr(priv, XIIC_INTR_BNB_MASK); |
| 204 | |
| 205 | writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0), |
| 206 | priv->base + XIIC_DTR_REG_OFFSET); |
| 207 | |
| 208 | if (nmsgs == 1) |
| 209 | /* very last, enable bus not busy as well */ |
| 210 | xiic_irq_clr(priv, XIIC_INTR_BNB_MASK); |
| 211 | |
| 212 | return xiic_read_rx(priv, msg, nmsgs); |
| 213 | } |
| 214 | |
| 215 | static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg, |
| 216 | int nmsgs) |
| 217 | { |
| 218 | struct xilinx_xiic_priv *priv = dev_get_priv(dev); |
| 219 | int ret; |
| 220 | |
| 221 | xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs); |
| 222 | xiic_fill_tx_fifo(priv, msg, nmsgs); |
| 223 | |
| 224 | ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, |
| 225 | XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true); |
| 226 | if (ret) |
| 227 | return ret; |
| 228 | |
| 229 | /* Clear any pending Tx empty, Tx Error and then enable them. */ |
| 230 | xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | |
| 231 | XIIC_INTR_BNB_MASK); |
| 232 | |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv) |
| 237 | { |
| 238 | u8 sr; |
| 239 | |
| 240 | for (sr = readb(priv->base + XIIC_SR_REG_OFFSET); |
| 241 | !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); |
| 242 | sr = readb(priv->base + XIIC_SR_REG_OFFSET)) |
| 243 | readb(priv->base + XIIC_DRR_REG_OFFSET); |
| 244 | } |
| 245 | |
| 246 | static void xiic_reinit(struct xilinx_xiic_priv *priv) |
| 247 | { |
| 248 | writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET); |
| 249 | |
| 250 | /* Set receive Fifo depth to maximum (zero based). */ |
| 251 | writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET); |
| 252 | |
| 253 | /* Reset Tx Fifo. */ |
| 254 | writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); |
| 255 | |
| 256 | /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ |
| 257 | writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); |
| 258 | |
| 259 | /* make sure RX fifo is empty */ |
| 260 | xiic_clear_rx_fifo(priv); |
| 261 | |
| 262 | /* Disable interrupts */ |
| 263 | writel(0, priv->base + XIIC_DGIER_OFFSET); |
| 264 | |
| 265 | xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK); |
| 266 | } |
| 267 | |
| 268 | static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) |
| 269 | { |
Melin Tomas | 362e4e6 | 2019-06-28 12:08:40 +0000 | [diff] [blame] | 270 | struct xilinx_xiic_priv *priv = dev_get_priv(dev); |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 271 | int ret = 0; |
| 272 | |
Melin Tomas | 362e4e6 | 2019-06-28 12:08:40 +0000 | [diff] [blame] | 273 | ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, |
| 274 | XIIC_SR_BUS_BUSY_MASK, false, 1000, true); |
| 275 | |
| 276 | if (ret == -ETIMEDOUT) |
| 277 | dev_err(dev, "timeout waiting for bus not busy condition\n"); |
| 278 | |
| 279 | if (ret) |
| 280 | return ret; |
| 281 | |
| 282 | xiic_reinit(priv); |
| 283 | |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 284 | for (; nmsgs > 0; nmsgs--, msg++) { |
| 285 | if (msg->flags & I2C_M_RD) |
| 286 | ret = xilinx_xiic_read_common(dev, msg, nmsgs); |
| 287 | else |
| 288 | ret = xilinx_xiic_write_common(dev, msg, nmsgs); |
| 289 | |
| 290 | if (ret) |
| 291 | return -EREMOTEIO; |
| 292 | } |
| 293 | |
| 294 | return ret; |
| 295 | } |
| 296 | |
| 297 | static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags) |
| 298 | { |
| 299 | struct xilinx_xiic_priv *priv = dev_get_priv(dev); |
| 300 | u32 reg; |
| 301 | int ret; |
| 302 | |
| 303 | xiic_reinit(priv); |
| 304 | |
| 305 | xilinx_xiic_set_addr(dev, addr, 0, 0, 1); |
| 306 | ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, |
| 307 | XIIC_SR_BUS_BUSY_MASK, false, 1000, true); |
| 308 | if (ret) |
| 309 | return ret; |
| 310 | |
| 311 | reg = readl(priv->base + XIIC_IISR_OFFSET); |
| 312 | if (reg & XIIC_INTR_TX_ERROR_MASK) |
| 313 | return -ENODEV; |
| 314 | |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | static int xilinx_xiic_set_speed(struct udevice *dev, uint speed) |
| 319 | { |
| 320 | return 0; |
| 321 | } |
| 322 | |
| 323 | static int xilinx_xiic_probe(struct udevice *dev) |
| 324 | { |
| 325 | struct xilinx_xiic_priv *priv = dev_get_priv(dev); |
| 326 | |
| 327 | priv->base = dev_read_addr_ptr(dev); |
| 328 | |
| 329 | writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); |
| 330 | xiic_reinit(priv); |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | static const struct dm_i2c_ops xilinx_xiic_ops = { |
| 336 | .xfer = xilinx_xiic_xfer, |
| 337 | .probe_chip = xilinx_xiic_probe_chip, |
| 338 | .set_bus_speed = xilinx_xiic_set_speed, |
| 339 | }; |
| 340 | |
| 341 | static const struct udevice_id xilinx_xiic_ids[] = { |
| 342 | { .compatible = "xlnx,xps-iic-2.00.a" }, |
| 343 | { } |
| 344 | }; |
| 345 | |
| 346 | U_BOOT_DRIVER(xilinx_xiic) = { |
| 347 | .name = "xilinx_axi_i2c", |
| 348 | .id = UCLASS_I2C, |
| 349 | .of_match = xilinx_xiic_ids, |
| 350 | .probe = xilinx_xiic_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 351 | .priv_auto = sizeof(struct xilinx_xiic_priv), |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 352 | .ops = &xilinx_xiic_ops, |
| 353 | }; |