Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
| 5 | * Keith Outwater, keith_outwater@mvis.com |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 6 | * |
| 7 | * Copyright (c) 2019 SED Systems, a division of Calian Ltd. |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * Configuration support for Xilinx Virtex2 devices. Based |
| 12 | * on spartan2.c (Rich Ireland, rireland@enterasys.com). |
| 13 | */ |
| 14 | |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 15 | #define LOG_CATEGORY UCLASS_FPGA |
| 16 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 17 | #include <common.h> |
Simon Glass | a73bda4 | 2015-11-08 23:47:45 -0700 | [diff] [blame] | 18 | #include <console.h> |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 19 | #include <log.h> |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 20 | #include <virtex2.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 21 | #include <linux/delay.h> |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 22 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 23 | /* |
Tom Rini | fe8f39a | 2022-12-04 10:03:29 -0500 | [diff] [blame] | 24 | * If the SelectMap interface can be overrun by the processor, enable |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 25 | * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 26 | * configuration file and add board-specific support for checking BUSY status. |
| 27 | * By default, assume that the SelectMap interface cannot be overrun. |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 28 | */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 29 | |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 30 | #ifndef CFG_FPGA_DELAY |
| 31 | #define CFG_FPGA_DELAY() |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 32 | #endif |
| 33 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 34 | /* |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 35 | * Check for errors during configuration by default |
| 36 | */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 37 | #ifndef CFG_SYS_FPGA_CHECK_ERROR |
| 38 | #define CFG_SYS_FPGA_CHECK_ERROR |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 39 | #endif |
| 40 | |
| 41 | /* |
| 42 | * The default timeout in mS for INIT_B to deassert after PROG_B has |
| 43 | * been deasserted. Per the latest Virtex II Handbook (page 347), the |
| 44 | * max time from PORG_B deassertion to INIT_B deassertion is 4uS per |
| 45 | * data frame for the XC2V8000. The XC2V8000 has 2860 data frames |
| 46 | * which yields 11.44 mS. So let's make it bigger in order to handle |
| 47 | * an XC2V1000, if anyone can ever get ahold of one. |
| 48 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 49 | #ifndef CFG_SYS_FPGA_WAIT_INIT |
| 50 | #define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 51 | #endif |
| 52 | |
| 53 | /* |
| 54 | * The default timeout for waiting for BUSY to deassert during configuration. |
| 55 | * This is normally not necessary since for most reasonable configuration |
| 56 | * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. |
| 57 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 58 | #ifndef CFG_SYS_FPGA_WAIT_BUSY |
| 59 | #define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 60 | #endif |
| 61 | |
| 62 | /* Default timeout for waiting for FPGA to enter operational mode after |
| 63 | * configuration data has been written. |
| 64 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 65 | #ifndef CFG_SYS_FPGA_WAIT_CONFIG |
| 66 | #define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 67 | #endif |
| 68 | |
Michal Simek | 25e1e2e | 2014-03-13 12:49:21 +0100 | [diff] [blame] | 69 | static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); |
| 70 | static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 71 | |
Michal Simek | 25e1e2e | 2014-03-13 12:49:21 +0100 | [diff] [blame] | 72 | static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); |
| 73 | static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 74 | |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 75 | static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, |
Oleksandr Suvorov | c0806cc | 2022-07-22 17:16:10 +0300 | [diff] [blame] | 76 | bitstream_type bstype, int flags) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 77 | { |
| 78 | int ret_val = FPGA_FAIL; |
| 79 | |
| 80 | switch (desc->iface) { |
| 81 | case slave_serial: |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 82 | log_debug("Launching Slave Serial Load\n"); |
Michal Simek | 9025888 | 2014-03-13 11:33:36 +0100 | [diff] [blame] | 83 | ret_val = virtex2_ss_load(desc, buf, bsize); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 84 | break; |
| 85 | |
| 86 | case slave_selectmap: |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 87 | log_debug("Launching Slave Parallel Load\n"); |
Michal Simek | 9025888 | 2014-03-13 11:33:36 +0100 | [diff] [blame] | 88 | ret_val = virtex2_ssm_load(desc, buf, bsize); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 89 | break; |
| 90 | |
| 91 | default: |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 92 | printf("%s: Unsupported interface type, %d\n", |
| 93 | __func__, desc->iface); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 94 | } |
| 95 | return ret_val; |
| 96 | } |
| 97 | |
Michal Simek | 75fafac | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 98 | static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 99 | { |
| 100 | int ret_val = FPGA_FAIL; |
| 101 | |
| 102 | switch (desc->iface) { |
| 103 | case slave_serial: |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 104 | log_debug("Launching Slave Serial Dump\n"); |
Michal Simek | 9025888 | 2014-03-13 11:33:36 +0100 | [diff] [blame] | 105 | ret_val = virtex2_ss_dump(desc, buf, bsize); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 106 | break; |
| 107 | |
| 108 | case slave_parallel: |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 109 | log_debug("Launching Slave Parallel Dump\n"); |
Michal Simek | 9025888 | 2014-03-13 11:33:36 +0100 | [diff] [blame] | 110 | ret_val = virtex2_ssm_dump(desc, buf, bsize); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 111 | break; |
| 112 | |
| 113 | default: |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 114 | printf("%s: Unsupported interface type, %d\n", |
| 115 | __func__, desc->iface); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 116 | } |
| 117 | return ret_val; |
| 118 | } |
| 119 | |
Michal Simek | 75fafac | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 120 | static int virtex2_info(xilinx_desc *desc) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 121 | { |
| 122 | return FPGA_SUCCESS; |
| 123 | } |
| 124 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 125 | /* |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 126 | * Virtex-II Slave SelectMap or Serial configuration loader. Configuration |
| 127 | * is as follows: |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 128 | * 1. Set the FPGA's PROG_B line low. |
| 129 | * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. |
| 130 | * 3. Write data to the SelectMap port. If INIT_B goes low at any time |
| 131 | * this process, a configuration error (most likely CRC failure) has |
| 132 | * ocurred. At this point a status word may be read from the |
| 133 | * SelectMap interface to determine the source of the problem (You |
Wolfgang Denk | ffb7756 | 2005-09-24 23:41:00 +0200 | [diff] [blame] | 134 | * could, for instance, put this in your 'abort' function handler). |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 135 | * 4. After all data has been written, test the state of the FPGA |
| 136 | * INIT_B and DONE lines. If both are high, configuration has |
| 137 | * succeeded. Congratulations! |
| 138 | */ |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 139 | static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 140 | { |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 141 | unsigned long ts; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 142 | |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 143 | log_debug("Start with interface functions @ 0x%p\n", fn); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 144 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 145 | if (!fn) { |
| 146 | printf("%s:%d: NULL Interface function table!\n", |
| 147 | __func__, __LINE__); |
| 148 | return FPGA_FAIL; |
| 149 | } |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 150 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 151 | /* Gotta split this one up (so the stack won't blow??) */ |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 152 | log_debug("Function Table:\n" |
| 153 | " base 0x%p\n" |
| 154 | " struct 0x%p\n" |
| 155 | " pre 0x%p\n" |
| 156 | " prog 0x%p\n" |
| 157 | " init 0x%p\n" |
| 158 | " error 0x%p\n", |
| 159 | &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); |
| 160 | log_debug(" clock 0x%p\n" |
| 161 | " cs 0x%p\n" |
| 162 | " write 0x%p\n" |
| 163 | " rdata 0x%p\n" |
| 164 | " wdata 0x%p\n" |
| 165 | " busy 0x%p\n" |
| 166 | " abort 0x%p\n" |
| 167 | " post 0x%p\n\n", |
| 168 | fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, |
| 169 | fn->busy, fn->abort, fn->post); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 170 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 172 | printf("Initializing FPGA Device %d...\n", cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 173 | #endif |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 174 | /* |
| 175 | * Run the pre configuration function if there is one. |
| 176 | */ |
| 177 | if (*fn->pre) |
| 178 | (*fn->pre)(cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 179 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 180 | /* |
| 181 | * Assert the program line. The minimum pulse width for |
| 182 | * Virtex II devices is 300 nS (Tprogram parameter in datasheet). |
| 183 | * There is no maximum value for the pulse width. Check to make |
| 184 | * sure that INIT_B goes low after assertion of PROG_B |
| 185 | */ |
| 186 | (*fn->pgm)(true, true, cookie); |
| 187 | udelay(10); |
| 188 | ts = get_timer(0); |
| 189 | do { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 190 | if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 191 | printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 192 | __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 193 | (*fn->abort)(cookie); |
| 194 | return FPGA_FAIL; |
| 195 | } |
| 196 | } while (!(*fn->init)(cookie)); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 197 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 198 | (*fn->pgm)(false, true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 199 | CFG_FPGA_DELAY(); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 200 | if (fn->clk) |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 201 | (*fn->clk)(true, true, cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 202 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 203 | /* |
| 204 | * Start a timer and wait for INIT_B to go high |
| 205 | */ |
| 206 | ts = get_timer(0); |
| 207 | do { |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 208 | CFG_FPGA_DELAY(); |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 209 | if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 210 | printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 211 | __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 212 | (*fn->abort)(cookie); |
| 213 | return FPGA_FAIL; |
| 214 | } |
| 215 | } while ((*fn->init)(cookie) && (*fn->busy)(cookie)); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 216 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 217 | if (fn->wr) |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 218 | (*fn->wr)(true, true, cookie); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 219 | if (fn->cs) |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 220 | (*fn->cs)(true, true, cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 221 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 222 | mdelay(10); |
| 223 | return FPGA_SUCCESS; |
| 224 | } |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 225 | |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 226 | static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 227 | int cookie) |
| 228 | { |
| 229 | int ret_val = FPGA_SUCCESS; |
Robert Hancock | 7b5140c | 2019-06-18 09:47:15 -0600 | [diff] [blame] | 230 | int num_done = 0; |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 231 | unsigned long ts; |
Wolfgang Denk | ffb7756 | 2005-09-24 23:41:00 +0200 | [diff] [blame] | 232 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 233 | /* |
| 234 | * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. |
| 235 | */ |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 236 | CFG_FPGA_DELAY(); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 237 | if (fn->cs) |
| 238 | (*fn->cs)(false, true, cookie); |
| 239 | if (fn->wr) |
| 240 | (*fn->wr)(false, true, cookie); |
Wolfgang Denk | ffb7756 | 2005-09-24 23:41:00 +0200 | [diff] [blame] | 241 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 242 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
| 243 | putc('\n'); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 244 | #endif |
Wolfgang Denk | ffb7756 | 2005-09-24 23:41:00 +0200 | [diff] [blame] | 245 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 246 | /* |
| 247 | * Check for successful configuration. FPGA INIT_B and DONE |
Robert Hancock | 7b5140c | 2019-06-18 09:47:15 -0600 | [diff] [blame] | 248 | * should both be high upon successful configuration. Continue pulsing |
| 249 | * clock with data set to all ones until DONE is asserted and for 8 |
| 250 | * clock cycles afterwards. |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 251 | */ |
| 252 | ts = get_timer(0); |
Robert Hancock | 7b5140c | 2019-06-18 09:47:15 -0600 | [diff] [blame] | 253 | while (true) { |
| 254 | if ((*fn->done)(cookie) == FPGA_SUCCESS && |
| 255 | !((*fn->init)(cookie))) { |
| 256 | if (num_done++ >= 8) |
| 257 | break; |
| 258 | } |
| 259 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 260 | if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) { |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 261 | printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 262 | __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 263 | (*fn->abort)(cookie); |
| 264 | ret_val = FPGA_FAIL; |
| 265 | break; |
| 266 | } |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 267 | if (fn->wbulkdata) { |
| 268 | unsigned char dummy = 0xff; |
| 269 | (*fn->wbulkdata)(&dummy, 1, true, cookie); |
| 270 | } else { |
| 271 | (*fn->wdata)(0xff, true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 272 | CFG_FPGA_DELAY(); |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 273 | (*fn->clk)(false, true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 274 | CFG_FPGA_DELAY(); |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 275 | (*fn->clk)(true, true, cookie); |
| 276 | } |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 277 | } |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 278 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 279 | if (ret_val == FPGA_SUCCESS) { |
| 280 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
| 281 | printf("Initialization of FPGA device %d complete\n", cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 282 | #endif |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 283 | /* |
| 284 | * Run the post configuration function if there is one. |
| 285 | */ |
| 286 | if (*fn->post) |
| 287 | (*fn->post)(cookie); |
| 288 | } else { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 290 | printf("** Initialization of FPGA device %d FAILED\n", |
| 291 | cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 292 | #endif |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 293 | } |
| 294 | return ret_val; |
| 295 | } |
| 296 | |
| 297 | static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) |
| 298 | { |
| 299 | int ret_val = FPGA_FAIL; |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 300 | xilinx_virtex2_slave_fns *fn = desc->iface_fns; |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 301 | size_t bytecount = 0; |
| 302 | unsigned char *data = (unsigned char *)buf; |
| 303 | int cookie = desc->cookie; |
| 304 | |
| 305 | ret_val = virtex2_slave_pre(fn, cookie); |
| 306 | if (ret_val != FPGA_SUCCESS) |
| 307 | return ret_val; |
| 308 | |
| 309 | /* |
| 310 | * Load the data byte by byte |
| 311 | */ |
| 312 | while (bytecount < bsize) { |
| 313 | #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
| 314 | if (ctrlc()) { |
| 315 | (*fn->abort)(cookie); |
| 316 | return FPGA_FAIL; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 317 | } |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 318 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 319 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 320 | if ((*fn->done)(cookie) == FPGA_SUCCESS) { |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 321 | log_debug("done went active early, bytecount = %zu\n", |
| 322 | bytecount); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 323 | break; |
| 324 | } |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 325 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 326 | #ifdef CFG_SYS_FPGA_CHECK_ERROR |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 327 | if ((*fn->init)(cookie)) { |
| 328 | printf("\n%s:%d: ** Error: INIT asserted during configuration\n", |
| 329 | __func__, __LINE__); |
| 330 | printf("%zu = buffer offset, %zu = buffer size\n", |
| 331 | bytecount, bsize); |
| 332 | (*fn->abort)(cookie); |
| 333 | return FPGA_FAIL; |
| 334 | } |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 335 | #endif |
| 336 | |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 337 | (*fn->wdata)(data[bytecount++], true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 338 | CFG_FPGA_DELAY(); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 339 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 340 | /* |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 341 | * Cycle the clock pin |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 342 | */ |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 343 | (*fn->clk)(false, true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 344 | CFG_FPGA_DELAY(); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 345 | (*fn->clk)(true, true, cookie); |
| 346 | |
| 347 | #ifdef CONFIG_SYS_FPGA_CHECK_BUSY |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 348 | ts = get_timer(0); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 349 | while ((*fn->busy)(cookie)) { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 350 | if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) { |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 351 | printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 352 | __func__, __LINE__, |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 353 | CFG_SYS_FPGA_WAIT_BUSY); |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 354 | (*fn->abort)(cookie); |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 355 | return FPGA_FAIL; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 356 | } |
| 357 | } |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 358 | #endif |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 359 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 360 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 361 | if (bytecount % (bsize / 40) == 0) |
| 362 | putc('.'); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 363 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 364 | } |
Robert Hancock | 8a7d663 | 2019-06-18 09:47:14 -0600 | [diff] [blame] | 365 | |
| 366 | return virtex2_slave_post(fn, cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 367 | } |
| 368 | |
| 369 | /* |
| 370 | * Read the FPGA configuration data |
| 371 | */ |
Michal Simek | 25e1e2e | 2014-03-13 12:49:21 +0100 | [diff] [blame] | 372 | static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 373 | { |
| 374 | int ret_val = FPGA_FAIL; |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 375 | xilinx_virtex2_slave_fns *fn = desc->iface_fns; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 376 | |
| 377 | if (fn) { |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 378 | unsigned char *data = (unsigned char *)buf; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 379 | size_t bytecount = 0; |
| 380 | int cookie = desc->cookie; |
| 381 | |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 382 | printf("Starting Dump of FPGA Device %d...\n", cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 383 | |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 384 | (*fn->cs)(true, true, cookie); |
| 385 | (*fn->clk)(true, true, cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 386 | |
| 387 | while (bytecount < bsize) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 388 | #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 389 | if (ctrlc()) { |
| 390 | (*fn->abort)(cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 391 | return FPGA_FAIL; |
| 392 | } |
| 393 | #endif |
| 394 | /* |
| 395 | * Cycle the clock and read the data |
| 396 | */ |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 397 | (*fn->clk)(false, true, cookie); |
| 398 | (*fn->clk)(true, true, cookie); |
| 399 | (*fn->rdata)(&data[bytecount++], cookie); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 400 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 401 | if (bytecount % (bsize / 40) == 0) |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 402 | putc('.'); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 403 | #endif |
| 404 | } |
| 405 | |
| 406 | /* |
| 407 | * Deassert CS_B and cycle the clock to deselect the device. |
| 408 | */ |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 409 | (*fn->cs)(false, false, cookie); |
| 410 | (*fn->clk)(false, true, cookie); |
| 411 | (*fn->clk)(true, true, cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 412 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 413 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 414 | putc('\n'); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 415 | #endif |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 416 | puts("Done.\n"); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 417 | } else { |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 418 | printf("%s:%d: NULL Interface function table!\n", |
| 419 | __func__, __LINE__); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 420 | } |
| 421 | return ret_val; |
| 422 | } |
| 423 | |
Michal Simek | 25e1e2e | 2014-03-13 12:49:21 +0100 | [diff] [blame] | 424 | static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 425 | { |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 426 | int ret_val = FPGA_FAIL; |
| 427 | xilinx_virtex2_slave_fns *fn = desc->iface_fns; |
| 428 | unsigned char *data = (unsigned char *)buf; |
| 429 | int cookie = desc->cookie; |
| 430 | |
| 431 | ret_val = virtex2_slave_pre(fn, cookie); |
| 432 | if (ret_val != FPGA_SUCCESS) |
| 433 | return ret_val; |
| 434 | |
| 435 | if (fn->wbulkdata) { |
| 436 | /* Load the data in a single chunk */ |
| 437 | (*fn->wbulkdata)(data, bsize, true, cookie); |
| 438 | } else { |
| 439 | size_t bytecount = 0; |
| 440 | |
| 441 | /* |
| 442 | * Load the data bit by bit |
| 443 | */ |
| 444 | while (bytecount < bsize) { |
| 445 | unsigned char curr_data = data[bytecount++]; |
| 446 | int bit; |
| 447 | |
| 448 | #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
| 449 | if (ctrlc()) { |
| 450 | (*fn->abort) (cookie); |
| 451 | return FPGA_FAIL; |
| 452 | } |
| 453 | #endif |
| 454 | |
| 455 | if ((*fn->done)(cookie) == FPGA_SUCCESS) { |
Alexander Dahl | 4b842e1 | 2022-10-07 14:20:03 +0200 | [diff] [blame] | 456 | log_debug("done went active early, bytecount = %zu\n", |
| 457 | bytecount); |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 458 | break; |
| 459 | } |
| 460 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 461 | #ifdef CFG_SYS_FPGA_CHECK_ERROR |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 462 | if ((*fn->init)(cookie)) { |
| 463 | printf("\n%s:%d: ** Error: INIT asserted during configuration\n", |
| 464 | __func__, __LINE__); |
| 465 | printf("%zu = buffer offset, %zu = buffer size\n", |
| 466 | bytecount, bsize); |
| 467 | (*fn->abort)(cookie); |
| 468 | return FPGA_FAIL; |
| 469 | } |
| 470 | #endif |
| 471 | |
| 472 | for (bit = 7; bit >= 0; --bit) { |
| 473 | unsigned char curr_bit = (curr_data >> bit) & 1; |
| 474 | (*fn->wdata)(curr_bit, true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 475 | CFG_FPGA_DELAY(); |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 476 | (*fn->clk)(false, true, cookie); |
Tom Rini | 88d86ec | 2022-12-04 10:03:57 -0500 | [diff] [blame] | 477 | CFG_FPGA_DELAY(); |
Robert Hancock | 0b88834 | 2019-06-18 09:47:16 -0600 | [diff] [blame] | 478 | (*fn->clk)(true, true, cookie); |
| 479 | } |
| 480 | |
| 481 | /* Slave serial never uses a busy pin */ |
| 482 | |
| 483 | #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
| 484 | if (bytecount % (bsize / 40) == 0) |
| 485 | putc('.'); |
| 486 | #endif |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | return virtex2_slave_post(fn, cookie); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 491 | } |
| 492 | |
Michal Simek | 25e1e2e | 2014-03-13 12:49:21 +0100 | [diff] [blame] | 493 | static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 494 | { |
Robert Hancock | 19b55dc | 2019-06-18 09:47:12 -0600 | [diff] [blame] | 495 | printf("%s: Slave Serial Dumping is unsupported\n", __func__); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 496 | return FPGA_FAIL; |
| 497 | } |
| 498 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 499 | /* vim: set ts=4 tw=78: */ |
Michal Simek | 75fafac | 2014-03-13 13:07:57 +0100 | [diff] [blame] | 500 | |
| 501 | struct xilinx_fpga_op virtex2_op = { |
| 502 | .load = virtex2_load, |
| 503 | .dump = virtex2_dump, |
| 504 | .info = virtex2_info, |
| 505 | }; |