blob: 46ccbb1d834d28458bfd37cab709ed240bb24635 [file] [log] [blame]
Simon Glass6eb4e3c2020-02-06 09:54:53 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
Tom Riniabb9a042024-05-18 20:20:43 -06007#include <common.h>
Simon Glass6eb4e3c2020-02-06 09:54:53 -07008#include <dm.h>
9#include <clk-uclass.h>
10#include <dt-bindings/clock/intel-clock.h>
11
12static ulong intel_clk_get_rate(struct clk *clk)
13{
Simon Glass6eb4e3c2020-02-06 09:54:53 -070014 switch (clk->id) {
15 case CLK_I2C:
16 /* Hard-coded to 133MHz on current platforms */
17 return 133333333;
18 default:
19 return -ENODEV;
20 }
Simon Glass6eb4e3c2020-02-06 09:54:53 -070021}
22
23static struct clk_ops intel_clk_ops = {
24 .get_rate = intel_clk_get_rate,
25};
26
27static const struct udevice_id intel_clk_ids[] = {
28 { .compatible = "intel,apl-clk" },
29 { }
30};
31
Simon Glass6646c572021-01-21 13:57:12 -070032U_BOOT_DRIVER(intel_apl_clk) = {
33 .name = "intel_apl_clk",
Simon Glass6eb4e3c2020-02-06 09:54:53 -070034 .id = UCLASS_CLK,
35 .of_match = intel_clk_ids,
36 .ops = &intel_clk_ops,
37};