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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada31adfc22016-01-19 13:55:28 +09002/*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada31adfc22016-01-19 13:55:28 +09004 */
5
Patrick Delaunay8767e792021-11-19 15:12:07 +01006#define LOG_CATEGORY UCLASS_CLK
7
Tom Riniabb9a042024-05-18 20:20:43 -06008#include <common.h>
Stephen Warrena9622432016-06-17 09:44:00 -06009#include <clk-uclass.h>
Simon Glass11c89f32017-05-17 17:18:03 -060010#include <dm.h>
Patrick Delaunay8767e792021-11-19 15:12:07 +010011#include <log.h>
Simon Glass95588622020-12-22 19:30:28 -070012#include <dm/device-internal.h>
Peng Fanec424a72019-07-31 07:01:39 +000013#include <linux/clk-provider.h>
Masahiro Yamada31adfc22016-01-19 13:55:28 +090014
Tero Kristode4ef9b2021-06-11 11:45:06 +030015#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
16#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
17
Stephen Warrena9622432016-06-17 09:44:00 -060018static ulong clk_fixed_rate_get_rate(struct clk *clk)
Masahiro Yamada31adfc22016-01-19 13:55:28 +090019{
Stephen Warrena9622432016-06-17 09:44:00 -060020 return to_clk_fixed_rate(clk->dev)->fixed_rate;
Masahiro Yamada31adfc22016-01-19 13:55:28 +090021}
22
developercdb0efd2020-01-09 11:35:08 +080023/* avoid clk_enable() return -ENOSYS */
24static int dummy_enable(struct clk *clk)
25{
26 return 0;
27}
28
Masahiro Yamada31adfc22016-01-19 13:55:28 +090029const struct clk_ops clk_fixed_rate_ops = {
30 .get_rate = clk_fixed_rate_get_rate,
developercdb0efd2020-01-09 11:35:08 +080031 .enable = dummy_enable,
Samuel Hollandd3196cb2021-10-12 19:40:29 -050032 .disable = dummy_enable,
Masahiro Yamada31adfc22016-01-19 13:55:28 +090033};
34
Simon Glassb95c7b92021-03-15 17:25:23 +130035void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
36 struct clk_fixed_rate *plat)
Masahiro Yamada31adfc22016-01-19 13:55:28 +090037{
Simon Glassb95c7b92021-03-15 17:25:23 +130038 struct clk *clk = &plat->clk;
Simon Glass6d70ba02021-08-07 07:24:06 -060039 if (CONFIG_IS_ENABLED(OF_REAL))
40 plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency",
41 0);
42
Lukasz Majewski9ded469272019-06-24 15:50:40 +020043 /* Make fixed rate clock accessible from higher level struct clk */
Simon Glass95588622020-12-22 19:30:28 -070044 /* FIXME: This is not allowed */
45 dev_set_uclass_priv(dev, clk);
Simon Glassb95c7b92021-03-15 17:25:23 +130046
Lukasz Majewski9ded469272019-06-24 15:50:40 +020047 clk->dev = dev;
Peng Fan30a6ebc2019-08-21 13:35:03 +000048 clk->enable_count = 0;
Simon Glassb95c7b92021-03-15 17:25:23 +130049}
50
Tero Kristode4ef9b2021-06-11 11:45:06 +030051static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
52{
53 return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
54}
55
56const struct clk_ops clk_fixed_rate_raw_ops = {
57 .get_rate = clk_fixed_rate_raw_get_rate,
58};
59
Simon Glassb95c7b92021-03-15 17:25:23 +130060static int clk_fixed_rate_of_to_plat(struct udevice *dev)
61{
62 clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
Masahiro Yamada31adfc22016-01-19 13:55:28 +090063
64 return 0;
65}
Tero Kristode4ef9b2021-06-11 11:45:06 +030066
67#if CONFIG_IS_ENABLED(CLK_CCF)
68struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
69 ulong rate)
70{
71 struct clk *clk;
72 struct clk_fixed_rate *fixed;
73 int ret;
74
75 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
76 if (!fixed)
77 return ERR_PTR(-ENOMEM);
78
79 fixed->fixed_rate = rate;
80
81 clk = &fixed->clk;
82
83 ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
84 if (ret) {
85 kfree(fixed);
86 return ERR_PTR(ret);
87 }
88
89 return clk;
90}
91#endif
Masahiro Yamada31adfc22016-01-19 13:55:28 +090092
93static const struct udevice_id clk_fixed_rate_match[] = {
94 {
95 .compatible = "fixed-clock",
96 },
97 { /* sentinel */ }
98};
99
Simon Glass6b927b12020-10-03 11:31:32 -0600100U_BOOT_DRIVER(fixed_clock) = {
101 .name = "fixed_clock",
Masahiro Yamada31adfc22016-01-19 13:55:28 +0900102 .id = UCLASS_CLK,
103 .of_match = clk_fixed_rate_match,
Simon Glassaad29ae2020-12-03 16:55:21 -0700104 .of_to_plat = clk_fixed_rate_of_to_plat,
Simon Glass71fa5b42020-12-03 16:55:18 -0700105 .plat_auto = sizeof(struct clk_fixed_rate),
Masahiro Yamada31adfc22016-01-19 13:55:28 +0900106 .ops = &clk_fixed_rate_ops,
Michal Simek34f67812020-09-16 13:20:55 +0200107 .flags = DM_FLAG_PRE_RELOC,
Masahiro Yamada31adfc22016-01-19 13:55:28 +0900108};
Tero Kristode4ef9b2021-06-11 11:45:06 +0300109
110U_BOOT_DRIVER(clk_fixed_rate_raw) = {
111 .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
112 .id = UCLASS_CLK,
113 .ops = &clk_fixed_rate_raw_ops,
114 .flags = DM_FLAG_PRE_RELOC,
115};