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Hans de Goedeb728aae2015-01-21 16:14:00 +01001/* DRAM parameters for auto dram configuration on sun5i and sun7i */
Hans de Goede7ee8cd12015-01-17 22:31:30 +01002
Tom Riniabb9a042024-05-18 20:20:43 -06003#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06004#include <init.h>
Hans de Goede7ee8cd12015-01-17 22:31:30 +01005#include <asm/arch/dram.h>
6
7static struct dram_para dram_para = {
8 .clock = CONFIG_DRAM_CLK,
Siarhei Siamashka47359bb2015-02-01 00:27:06 +02009 .mbus_clock = CONFIG_DRAM_MBUS_CLK,
Giulio Benetti0fe7a5f2021-12-03 00:57:54 +010010 .type = DRAM_MEMORY_TYPE_DDR3,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010011 .rank_num = 1,
12 .density = 0,
13 .io_width = 0,
14 .bus_width = 0,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010015 .zq = CONFIG_DRAM_ZQ,
Hans de Goedeffdc05c2015-05-13 15:00:46 +020016 .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
Hans de Goede7ee8cd12015-01-17 22:31:30 +010017 .size = 0,
Siarhei Siamashka9900db12015-02-01 00:27:05 +020018#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
19 .cas = 9,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010020 .tpr0 = 0x42d899b7,
21 .tpr1 = 0xa090,
22 .tpr2 = 0x22a00,
Siarhei Siamashka9900db12015-02-01 00:27:05 +020023 .emr2 = 0x10,
24#else
25# include "dram_timings_sun4i.h"
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020026 .active_windowing = 1,
Siarhei Siamashka9900db12015-02-01 00:27:05 +020027#endif
Adam Sampsone954e922015-02-23 20:44:10 +000028 .tpr3 = CONFIG_DRAM_TPR3,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010029 .tpr4 = 0,
30 .tpr5 = 0,
31 .emr1 = CONFIG_DRAM_EMR1,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010032 .emr3 = 0,
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020033 .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010034};
35
36unsigned long sunxi_dram_init(void)
37{
38 return dramc_init(&dram_para);
39}