Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 |
Mario Six | b489358 | 2018-03-06 08:04:58 +0100 | [diff] [blame] | 4 | * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 7 | #include <common.h> |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 8 | #include <command.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 9 | #include <init.h> |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 10 | #include <asm/processor.h> |
| 11 | #include <asm/io.h> |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 14 | |
| 15 | #include "mpc8308.h" |
| 16 | #include <gdsys_fpga.h> |
| 17 | |
| 18 | #define REFLECTION_TESTPATTERN 0xdede |
| 19 | #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) |
| 20 | |
| 21 | #ifdef CONFIG_SYS_FPGA_NO_RFL_HI |
| 22 | #define REFLECTION_TESTREG reflection_low |
| 23 | #else |
| 24 | #define REFLECTION_TESTREG reflection_high |
| 25 | #endif |
| 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
Mario Six | 7851021 | 2019-03-29 10:18:10 +0100 | [diff] [blame] | 29 | #ifdef CONFIG_GDSYS_LEGACY_DRIVERS |
Mario Six | ae0feaa | 2019-03-29 10:18:07 +0100 | [diff] [blame] | 30 | /* as gpio output status cannot be read back, we have to buffer it locally */ |
| 31 | u32 gpio0_out; |
| 32 | |
| 33 | void setbits_gpio0_out(u32 mask) |
| 34 | { |
| 35 | immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
| 36 | |
| 37 | gpio0_out |= mask; |
| 38 | out_be32(&immr->gpio[0].dat, gpio0_out); |
| 39 | } |
| 40 | |
| 41 | void clrbits_gpio0_out(u32 mask) |
| 42 | { |
| 43 | immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
| 44 | |
| 45 | gpio0_out &= ~mask; |
| 46 | out_be32(&immr->gpio[0].dat, gpio0_out); |
| 47 | } |
| 48 | |
Mario Six | 3809c47 | 2019-03-29 10:18:06 +0100 | [diff] [blame] | 49 | int get_fpga_state(uint dev) |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 50 | { |
| 51 | return gd->arch.fpga_state[dev]; |
| 52 | } |
| 53 | |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 54 | int board_early_init_f(void) |
| 55 | { |
Mario Six | 3809c47 | 2019-03-29 10:18:06 +0100 | [diff] [blame] | 56 | uint k; |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 57 | |
| 58 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
| 59 | gd->arch.fpga_state[k] = 0; |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | int board_early_init_r(void) |
| 65 | { |
Mario Six | 3809c47 | 2019-03-29 10:18:06 +0100 | [diff] [blame] | 66 | uint k; |
| 67 | uint ctr; |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 68 | |
| 69 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
| 70 | gd->arch.fpga_state[k] = 0; |
| 71 | |
| 72 | /* |
| 73 | * reset FPGA |
| 74 | */ |
| 75 | mpc8308_init(); |
| 76 | |
| 77 | mpc8308_set_fpga_reset(1); |
| 78 | |
| 79 | mpc8308_setup_hw(); |
| 80 | |
| 81 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
| 82 | ctr = 0; |
| 83 | while (!mpc8308_get_fpga_done(k)) { |
Mario Six | 3809c47 | 2019-03-29 10:18:06 +0100 | [diff] [blame] | 84 | mdelay(100); |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 85 | if (ctr++ > 5) { |
| 86 | gd->arch.fpga_state[k] |= |
| 87 | FPGA_STATE_DONE_FAILED; |
| 88 | break; |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | udelay(10); |
| 94 | |
| 95 | mpc8308_set_fpga_reset(0); |
| 96 | |
| 97 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
| 98 | /* |
| 99 | * wait for fpga out of reset |
| 100 | */ |
| 101 | ctr = 0; |
| 102 | while (1) { |
| 103 | u16 val; |
| 104 | |
| 105 | FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); |
| 106 | |
| 107 | FPGA_GET_REG(k, REFLECTION_TESTREG, &val); |
| 108 | if (val == REFLECTION_TESTPATTERN_INV) |
| 109 | break; |
| 110 | |
Mario Six | 3809c47 | 2019-03-29 10:18:06 +0100 | [diff] [blame] | 111 | mdelay(100); |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 112 | if (ctr++ > 5) { |
| 113 | gd->arch.fpga_state[k] |= |
| 114 | FPGA_STATE_REFLECTION_FAILED; |
| 115 | break; |
| 116 | } |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | return 0; |
| 121 | } |
Mario Six | 7851021 | 2019-03-29 10:18:10 +0100 | [diff] [blame] | 122 | #endif |