Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H |
| 7 | #define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H |
| 8 | |
| 9 | #define GPLL0 0 |
| 10 | #define GPLL0_MAIN 1 |
| 11 | #define GCC_SLEEP_CLK_SRC 2 |
| 12 | #define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 |
| 13 | #define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 |
| 14 | #define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 |
| 15 | #define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 |
| 16 | #define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 |
| 17 | #define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 |
| 18 | #define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 |
| 19 | #define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 |
| 20 | #define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 |
| 21 | #define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 |
| 22 | #define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 |
| 23 | #define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 |
| 24 | #define BLSP1_UART1_APPS_CLK_SRC 15 |
| 25 | #define BLSP1_UART2_APPS_CLK_SRC 16 |
| 26 | #define BLSP1_UART3_APPS_CLK_SRC 17 |
| 27 | #define BLSP1_UART4_APPS_CLK_SRC 18 |
| 28 | #define BLSP1_UART5_APPS_CLK_SRC 19 |
| 29 | #define BLSP1_UART6_APPS_CLK_SRC 20 |
| 30 | #define GCC_BLSP1_AHB_CLK 21 |
| 31 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 |
| 32 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 |
| 33 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 |
| 34 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 |
| 35 | #define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 |
| 36 | #define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 |
| 37 | #define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 |
| 38 | #define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 |
| 39 | #define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 |
| 40 | #define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 |
| 41 | #define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 |
| 42 | #define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 |
| 43 | #define GCC_BLSP1_UART1_APPS_CLK 34 |
| 44 | #define GCC_BLSP1_UART2_APPS_CLK 35 |
| 45 | #define GCC_BLSP1_UART3_APPS_CLK 36 |
| 46 | #define GCC_BLSP1_UART4_APPS_CLK 37 |
| 47 | #define GCC_BLSP1_UART5_APPS_CLK 38 |
| 48 | #define GCC_BLSP1_UART6_APPS_CLK 39 |
| 49 | #define GCC_PRNG_AHB_CLK 40 |
| 50 | #define GCC_QPIC_AHB_CLK 41 |
| 51 | #define GCC_QPIC_CLK 42 |
| 52 | #define PCNOC_BFDCD_CLK_SRC 43 |
| 53 | #define GPLL2_MAIN 44 |
| 54 | #define GPLL2 45 |
| 55 | #define GPLL4_MAIN 46 |
| 56 | #define GPLL4 47 |
| 57 | #define GPLL6_MAIN 48 |
| 58 | #define GPLL6 49 |
| 59 | #define UBI32_PLL_MAIN 50 |
| 60 | #define UBI32_PLL 51 |
| 61 | #define NSS_CRYPTO_PLL_MAIN 52 |
| 62 | #define NSS_CRYPTO_PLL 53 |
| 63 | #define PCIE0_AXI_CLK_SRC 54 |
| 64 | #define PCIE0_AUX_CLK_SRC 55 |
| 65 | #define PCIE0_PIPE_CLK_SRC 56 |
| 66 | #define PCIE1_AXI_CLK_SRC 57 |
| 67 | #define PCIE1_AUX_CLK_SRC 58 |
| 68 | #define PCIE1_PIPE_CLK_SRC 59 |
| 69 | #define SDCC1_APPS_CLK_SRC 60 |
| 70 | #define SDCC1_ICE_CORE_CLK_SRC 61 |
| 71 | #define SDCC2_APPS_CLK_SRC 62 |
| 72 | #define USB0_MASTER_CLK_SRC 63 |
| 73 | #define USB0_AUX_CLK_SRC 64 |
| 74 | #define USB0_MOCK_UTMI_CLK_SRC 65 |
| 75 | #define USB0_PIPE_CLK_SRC 66 |
| 76 | #define USB1_MASTER_CLK_SRC 67 |
| 77 | #define USB1_AUX_CLK_SRC 68 |
| 78 | #define USB1_MOCK_UTMI_CLK_SRC 69 |
| 79 | #define USB1_PIPE_CLK_SRC 70 |
| 80 | #define GCC_XO_CLK_SRC 71 |
| 81 | #define SYSTEM_NOC_BFDCD_CLK_SRC 72 |
| 82 | #define NSS_CE_CLK_SRC 73 |
| 83 | #define NSS_NOC_BFDCD_CLK_SRC 74 |
| 84 | #define NSS_CRYPTO_CLK_SRC 75 |
| 85 | #define NSS_UBI0_CLK_SRC 76 |
| 86 | #define NSS_UBI0_DIV_CLK_SRC 77 |
| 87 | #define NSS_UBI1_CLK_SRC 78 |
| 88 | #define NSS_UBI1_DIV_CLK_SRC 79 |
| 89 | #define UBI_MPT_CLK_SRC 80 |
| 90 | #define NSS_IMEM_CLK_SRC 81 |
| 91 | #define NSS_PPE_CLK_SRC 82 |
| 92 | #define NSS_PORT1_RX_CLK_SRC 83 |
| 93 | #define NSS_PORT1_RX_DIV_CLK_SRC 84 |
| 94 | #define NSS_PORT1_TX_CLK_SRC 85 |
| 95 | #define NSS_PORT1_TX_DIV_CLK_SRC 86 |
| 96 | #define NSS_PORT2_RX_CLK_SRC 87 |
| 97 | #define NSS_PORT2_RX_DIV_CLK_SRC 88 |
| 98 | #define NSS_PORT2_TX_CLK_SRC 89 |
| 99 | #define NSS_PORT2_TX_DIV_CLK_SRC 90 |
| 100 | #define NSS_PORT3_RX_CLK_SRC 91 |
| 101 | #define NSS_PORT3_RX_DIV_CLK_SRC 92 |
| 102 | #define NSS_PORT3_TX_CLK_SRC 93 |
| 103 | #define NSS_PORT3_TX_DIV_CLK_SRC 94 |
| 104 | #define NSS_PORT4_RX_CLK_SRC 95 |
| 105 | #define NSS_PORT4_RX_DIV_CLK_SRC 96 |
| 106 | #define NSS_PORT4_TX_CLK_SRC 97 |
| 107 | #define NSS_PORT4_TX_DIV_CLK_SRC 98 |
| 108 | #define NSS_PORT5_RX_CLK_SRC 99 |
| 109 | #define NSS_PORT5_RX_DIV_CLK_SRC 100 |
| 110 | #define NSS_PORT5_TX_CLK_SRC 101 |
| 111 | #define NSS_PORT5_TX_DIV_CLK_SRC 102 |
| 112 | #define NSS_PORT6_RX_CLK_SRC 103 |
| 113 | #define NSS_PORT6_RX_DIV_CLK_SRC 104 |
| 114 | #define NSS_PORT6_TX_CLK_SRC 105 |
| 115 | #define NSS_PORT6_TX_DIV_CLK_SRC 106 |
| 116 | #define CRYPTO_CLK_SRC 107 |
| 117 | #define GP1_CLK_SRC 108 |
| 118 | #define GP2_CLK_SRC 109 |
| 119 | #define GP3_CLK_SRC 110 |
| 120 | #define GCC_PCIE0_AHB_CLK 111 |
| 121 | #define GCC_PCIE0_AUX_CLK 112 |
| 122 | #define GCC_PCIE0_AXI_M_CLK 113 |
| 123 | #define GCC_PCIE0_AXI_S_CLK 114 |
| 124 | #define GCC_PCIE0_PIPE_CLK 115 |
| 125 | #define GCC_SYS_NOC_PCIE0_AXI_CLK 116 |
| 126 | #define GCC_PCIE1_AHB_CLK 117 |
| 127 | #define GCC_PCIE1_AUX_CLK 118 |
| 128 | #define GCC_PCIE1_AXI_M_CLK 119 |
| 129 | #define GCC_PCIE1_AXI_S_CLK 120 |
| 130 | #define GCC_PCIE1_PIPE_CLK 121 |
| 131 | #define GCC_SYS_NOC_PCIE1_AXI_CLK 122 |
| 132 | #define GCC_USB0_AUX_CLK 123 |
| 133 | #define GCC_SYS_NOC_USB0_AXI_CLK 124 |
| 134 | #define GCC_USB0_MASTER_CLK 125 |
| 135 | #define GCC_USB0_MOCK_UTMI_CLK 126 |
| 136 | #define GCC_USB0_PHY_CFG_AHB_CLK 127 |
| 137 | #define GCC_USB0_PIPE_CLK 128 |
| 138 | #define GCC_USB0_SLEEP_CLK 129 |
| 139 | #define GCC_USB1_AUX_CLK 130 |
| 140 | #define GCC_SYS_NOC_USB1_AXI_CLK 131 |
| 141 | #define GCC_USB1_MASTER_CLK 132 |
| 142 | #define GCC_USB1_MOCK_UTMI_CLK 133 |
| 143 | #define GCC_USB1_PHY_CFG_AHB_CLK 134 |
| 144 | #define GCC_USB1_PIPE_CLK 135 |
| 145 | #define GCC_USB1_SLEEP_CLK 136 |
| 146 | #define GCC_SDCC1_AHB_CLK 137 |
| 147 | #define GCC_SDCC1_APPS_CLK 138 |
| 148 | #define GCC_SDCC1_ICE_CORE_CLK 139 |
| 149 | #define GCC_SDCC2_AHB_CLK 140 |
| 150 | #define GCC_SDCC2_APPS_CLK 141 |
| 151 | #define GCC_MEM_NOC_NSS_AXI_CLK 142 |
| 152 | #define GCC_NSS_CE_APB_CLK 143 |
| 153 | #define GCC_NSS_CE_AXI_CLK 144 |
| 154 | #define GCC_NSS_CFG_CLK 145 |
| 155 | #define GCC_NSS_CRYPTO_CLK 146 |
| 156 | #define GCC_NSS_CSR_CLK 147 |
| 157 | #define GCC_NSS_EDMA_CFG_CLK 148 |
| 158 | #define GCC_NSS_EDMA_CLK 149 |
| 159 | #define GCC_NSS_IMEM_CLK 150 |
| 160 | #define GCC_NSS_NOC_CLK 151 |
| 161 | #define GCC_NSS_PPE_BTQ_CLK 152 |
| 162 | #define GCC_NSS_PPE_CFG_CLK 153 |
| 163 | #define GCC_NSS_PPE_CLK 154 |
| 164 | #define GCC_NSS_PPE_IPE_CLK 155 |
| 165 | #define GCC_NSS_PTP_REF_CLK 156 |
| 166 | #define GCC_NSSNOC_CE_APB_CLK 157 |
| 167 | #define GCC_NSSNOC_CE_AXI_CLK 158 |
| 168 | #define GCC_NSSNOC_CRYPTO_CLK 159 |
| 169 | #define GCC_NSSNOC_PPE_CFG_CLK 160 |
| 170 | #define GCC_NSSNOC_PPE_CLK 161 |
| 171 | #define GCC_NSSNOC_QOSGEN_REF_CLK 162 |
| 172 | #define GCC_NSSNOC_SNOC_CLK 163 |
| 173 | #define GCC_NSSNOC_TIMEOUT_REF_CLK 164 |
| 174 | #define GCC_NSSNOC_UBI0_AHB_CLK 165 |
| 175 | #define GCC_NSSNOC_UBI1_AHB_CLK 166 |
| 176 | #define GCC_UBI0_AHB_CLK 167 |
| 177 | #define GCC_UBI0_AXI_CLK 168 |
| 178 | #define GCC_UBI0_NC_AXI_CLK 169 |
| 179 | #define GCC_UBI0_CORE_CLK 170 |
| 180 | #define GCC_UBI0_MPT_CLK 171 |
| 181 | #define GCC_UBI1_AHB_CLK 172 |
| 182 | #define GCC_UBI1_AXI_CLK 173 |
| 183 | #define GCC_UBI1_NC_AXI_CLK 174 |
| 184 | #define GCC_UBI1_CORE_CLK 175 |
| 185 | #define GCC_UBI1_MPT_CLK 176 |
| 186 | #define GCC_CMN_12GPLL_AHB_CLK 177 |
| 187 | #define GCC_CMN_12GPLL_SYS_CLK 178 |
| 188 | #define GCC_MDIO_AHB_CLK 179 |
| 189 | #define GCC_UNIPHY0_AHB_CLK 180 |
| 190 | #define GCC_UNIPHY0_SYS_CLK 181 |
| 191 | #define GCC_UNIPHY1_AHB_CLK 182 |
| 192 | #define GCC_UNIPHY1_SYS_CLK 183 |
| 193 | #define GCC_UNIPHY2_AHB_CLK 184 |
| 194 | #define GCC_UNIPHY2_SYS_CLK 185 |
| 195 | #define GCC_NSS_PORT1_RX_CLK 186 |
| 196 | #define GCC_NSS_PORT1_TX_CLK 187 |
| 197 | #define GCC_NSS_PORT2_RX_CLK 188 |
| 198 | #define GCC_NSS_PORT2_TX_CLK 189 |
| 199 | #define GCC_NSS_PORT3_RX_CLK 190 |
| 200 | #define GCC_NSS_PORT3_TX_CLK 191 |
| 201 | #define GCC_NSS_PORT4_RX_CLK 192 |
| 202 | #define GCC_NSS_PORT4_TX_CLK 193 |
| 203 | #define GCC_NSS_PORT5_RX_CLK 194 |
| 204 | #define GCC_NSS_PORT5_TX_CLK 195 |
| 205 | #define GCC_NSS_PORT6_RX_CLK 196 |
| 206 | #define GCC_NSS_PORT6_TX_CLK 197 |
| 207 | #define GCC_PORT1_MAC_CLK 198 |
| 208 | #define GCC_PORT2_MAC_CLK 199 |
| 209 | #define GCC_PORT3_MAC_CLK 200 |
| 210 | #define GCC_PORT4_MAC_CLK 201 |
| 211 | #define GCC_PORT5_MAC_CLK 202 |
| 212 | #define GCC_PORT6_MAC_CLK 203 |
| 213 | #define GCC_UNIPHY0_PORT1_RX_CLK 204 |
| 214 | #define GCC_UNIPHY0_PORT1_TX_CLK 205 |
| 215 | #define GCC_UNIPHY0_PORT2_RX_CLK 206 |
| 216 | #define GCC_UNIPHY0_PORT2_TX_CLK 207 |
| 217 | #define GCC_UNIPHY0_PORT3_RX_CLK 208 |
| 218 | #define GCC_UNIPHY0_PORT3_TX_CLK 209 |
| 219 | #define GCC_UNIPHY0_PORT4_RX_CLK 210 |
| 220 | #define GCC_UNIPHY0_PORT4_TX_CLK 211 |
| 221 | #define GCC_UNIPHY0_PORT5_RX_CLK 212 |
| 222 | #define GCC_UNIPHY0_PORT5_TX_CLK 213 |
| 223 | #define GCC_UNIPHY1_PORT5_RX_CLK 214 |
| 224 | #define GCC_UNIPHY1_PORT5_TX_CLK 215 |
| 225 | #define GCC_UNIPHY2_PORT6_RX_CLK 216 |
| 226 | #define GCC_UNIPHY2_PORT6_TX_CLK 217 |
| 227 | #define GCC_CRYPTO_AHB_CLK 218 |
| 228 | #define GCC_CRYPTO_AXI_CLK 219 |
| 229 | #define GCC_CRYPTO_CLK 220 |
| 230 | #define GCC_GP1_CLK 221 |
| 231 | #define GCC_GP2_CLK 222 |
| 232 | #define GCC_GP3_CLK 223 |
| 233 | #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 |
| 234 | #define GCC_PCIE0_RCHNG_CLK_SRC 225 |
| 235 | #define GCC_PCIE0_RCHNG_CLK 226 |
| 236 | #define GCC_CRYPTO_PPE_CLK 227 |
| 237 | |
| 238 | #define GCC_BLSP1_BCR 0 |
| 239 | #define GCC_BLSP1_QUP1_BCR 1 |
| 240 | #define GCC_BLSP1_UART1_BCR 2 |
| 241 | #define GCC_BLSP1_QUP2_BCR 3 |
| 242 | #define GCC_BLSP1_UART2_BCR 4 |
| 243 | #define GCC_BLSP1_QUP3_BCR 5 |
| 244 | #define GCC_BLSP1_UART3_BCR 6 |
| 245 | #define GCC_BLSP1_QUP4_BCR 7 |
| 246 | #define GCC_BLSP1_UART4_BCR 8 |
| 247 | #define GCC_BLSP1_QUP5_BCR 9 |
| 248 | #define GCC_BLSP1_UART5_BCR 10 |
| 249 | #define GCC_BLSP1_QUP6_BCR 11 |
| 250 | #define GCC_BLSP1_UART6_BCR 12 |
| 251 | #define GCC_IMEM_BCR 13 |
| 252 | #define GCC_SMMU_BCR 14 |
| 253 | #define GCC_APSS_TCU_BCR 15 |
| 254 | #define GCC_SMMU_XPU_BCR 16 |
| 255 | #define GCC_PCNOC_TBU_BCR 17 |
| 256 | #define GCC_SMMU_CFG_BCR 18 |
| 257 | #define GCC_PRNG_BCR 19 |
| 258 | #define GCC_BOOT_ROM_BCR 20 |
| 259 | #define GCC_CRYPTO_BCR 21 |
| 260 | #define GCC_WCSS_BCR 22 |
| 261 | #define GCC_WCSS_Q6_BCR 23 |
| 262 | #define GCC_NSS_BCR 24 |
| 263 | #define GCC_SEC_CTRL_BCR 25 |
| 264 | #define GCC_ADSS_BCR 26 |
| 265 | #define GCC_DDRSS_BCR 27 |
| 266 | #define GCC_SYSTEM_NOC_BCR 28 |
| 267 | #define GCC_PCNOC_BCR 29 |
| 268 | #define GCC_TCSR_BCR 30 |
| 269 | #define GCC_QDSS_BCR 31 |
| 270 | #define GCC_DCD_BCR 32 |
| 271 | #define GCC_MSG_RAM_BCR 33 |
| 272 | #define GCC_MPM_BCR 34 |
| 273 | #define GCC_SPMI_BCR 35 |
| 274 | #define GCC_SPDM_BCR 36 |
| 275 | #define GCC_RBCPR_BCR 37 |
| 276 | #define GCC_RBCPR_MX_BCR 38 |
| 277 | #define GCC_TLMM_BCR 39 |
| 278 | #define GCC_RBCPR_WCSS_BCR 40 |
| 279 | #define GCC_USB0_PHY_BCR 41 |
| 280 | #define GCC_USB3PHY_0_PHY_BCR 42 |
| 281 | #define GCC_USB0_BCR 43 |
| 282 | #define GCC_USB1_PHY_BCR 44 |
| 283 | #define GCC_USB3PHY_1_PHY_BCR 45 |
| 284 | #define GCC_USB1_BCR 46 |
| 285 | #define GCC_QUSB2_0_PHY_BCR 47 |
| 286 | #define GCC_QUSB2_1_PHY_BCR 48 |
| 287 | #define GCC_SDCC1_BCR 49 |
| 288 | #define GCC_SDCC2_BCR 50 |
| 289 | #define GCC_SNOC_BUS_TIMEOUT0_BCR 51 |
| 290 | #define GCC_SNOC_BUS_TIMEOUT2_BCR 52 |
| 291 | #define GCC_SNOC_BUS_TIMEOUT3_BCR 53 |
| 292 | #define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 |
| 293 | #define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 |
| 294 | #define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 |
| 295 | #define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 |
| 296 | #define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 |
| 297 | #define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 |
| 298 | #define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 |
| 299 | #define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 |
| 300 | #define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 |
| 301 | #define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 |
| 302 | #define GCC_UNIPHY0_BCR 64 |
| 303 | #define GCC_UNIPHY1_BCR 65 |
| 304 | #define GCC_UNIPHY2_BCR 66 |
| 305 | #define GCC_CMN_12GPLL_BCR 67 |
| 306 | #define GCC_QPIC_BCR 68 |
| 307 | #define GCC_MDIO_BCR 69 |
| 308 | #define GCC_PCIE1_TBU_BCR 70 |
| 309 | #define GCC_WCSS_CORE_TBU_BCR 71 |
| 310 | #define GCC_WCSS_Q6_TBU_BCR 72 |
| 311 | #define GCC_USB0_TBU_BCR 73 |
| 312 | #define GCC_USB1_TBU_BCR 74 |
| 313 | #define GCC_PCIE0_TBU_BCR 75 |
| 314 | #define GCC_NSS_NOC_TBU_BCR 76 |
| 315 | #define GCC_PCIE0_BCR 77 |
| 316 | #define GCC_PCIE0_PHY_BCR 78 |
| 317 | #define GCC_PCIE0PHY_PHY_BCR 79 |
| 318 | #define GCC_PCIE0_LINK_DOWN_BCR 80 |
| 319 | #define GCC_PCIE1_BCR 81 |
| 320 | #define GCC_PCIE1_PHY_BCR 82 |
| 321 | #define GCC_PCIE1PHY_PHY_BCR 83 |
| 322 | #define GCC_PCIE1_LINK_DOWN_BCR 84 |
| 323 | #define GCC_DCC_BCR 85 |
| 324 | #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 |
| 325 | #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 |
| 326 | #define GCC_SMMU_CATS_BCR 88 |
| 327 | #define GCC_UBI0_AXI_ARES 89 |
| 328 | #define GCC_UBI0_AHB_ARES 90 |
| 329 | #define GCC_UBI0_NC_AXI_ARES 91 |
| 330 | #define GCC_UBI0_DBG_ARES 92 |
| 331 | #define GCC_UBI0_CORE_CLAMP_ENABLE 93 |
| 332 | #define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 |
| 333 | #define GCC_UBI1_AXI_ARES 95 |
| 334 | #define GCC_UBI1_AHB_ARES 96 |
| 335 | #define GCC_UBI1_NC_AXI_ARES 97 |
| 336 | #define GCC_UBI1_DBG_ARES 98 |
| 337 | #define GCC_UBI1_CORE_CLAMP_ENABLE 99 |
| 338 | #define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 |
| 339 | #define GCC_NSS_CFG_ARES 101 |
| 340 | #define GCC_NSS_IMEM_ARES 102 |
| 341 | #define GCC_NSS_NOC_ARES 103 |
| 342 | #define GCC_NSS_CRYPTO_ARES 104 |
| 343 | #define GCC_NSS_CSR_ARES 105 |
| 344 | #define GCC_NSS_CE_APB_ARES 106 |
| 345 | #define GCC_NSS_CE_AXI_ARES 107 |
| 346 | #define GCC_NSSNOC_CE_APB_ARES 108 |
| 347 | #define GCC_NSSNOC_CE_AXI_ARES 109 |
| 348 | #define GCC_NSSNOC_UBI0_AHB_ARES 110 |
| 349 | #define GCC_NSSNOC_UBI1_AHB_ARES 111 |
| 350 | #define GCC_NSSNOC_SNOC_ARES 112 |
| 351 | #define GCC_NSSNOC_CRYPTO_ARES 113 |
| 352 | #define GCC_NSSNOC_ATB_ARES 114 |
| 353 | #define GCC_NSSNOC_QOSGEN_REF_ARES 115 |
| 354 | #define GCC_NSSNOC_TIMEOUT_REF_ARES 116 |
| 355 | #define GCC_PCIE0_PIPE_ARES 117 |
| 356 | #define GCC_PCIE0_SLEEP_ARES 118 |
| 357 | #define GCC_PCIE0_CORE_STICKY_ARES 119 |
| 358 | #define GCC_PCIE0_AXI_MASTER_ARES 120 |
| 359 | #define GCC_PCIE0_AXI_SLAVE_ARES 121 |
| 360 | #define GCC_PCIE0_AHB_ARES 122 |
| 361 | #define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 |
| 362 | #define GCC_PCIE1_PIPE_ARES 124 |
| 363 | #define GCC_PCIE1_SLEEP_ARES 125 |
| 364 | #define GCC_PCIE1_CORE_STICKY_ARES 126 |
| 365 | #define GCC_PCIE1_AXI_MASTER_ARES 127 |
| 366 | #define GCC_PCIE1_AXI_SLAVE_ARES 128 |
| 367 | #define GCC_PCIE1_AHB_ARES 129 |
| 368 | #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 |
| 369 | #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 |
| 370 | #define GCC_PPE_FULL_RESET 132 |
| 371 | #define GCC_UNIPHY0_SOFT_RESET 133 |
| 372 | #define GCC_UNIPHY0_XPCS_RESET 134 |
| 373 | #define GCC_UNIPHY1_SOFT_RESET 135 |
| 374 | #define GCC_UNIPHY1_XPCS_RESET 136 |
| 375 | #define GCC_UNIPHY2_SOFT_RESET 137 |
| 376 | #define GCC_UNIPHY2_XPCS_RESET 138 |
| 377 | #define GCC_EDMA_HW_RESET 139 |
| 378 | #define GCC_NSSPORT1_RESET 140 |
| 379 | #define GCC_NSSPORT2_RESET 141 |
| 380 | #define GCC_NSSPORT3_RESET 142 |
| 381 | #define GCC_NSSPORT4_RESET 143 |
| 382 | #define GCC_NSSPORT5_RESET 144 |
| 383 | #define GCC_NSSPORT6_RESET 145 |
| 384 | |
| 385 | #define USB0_GDSC 0 |
| 386 | #define USB1_GDSC 1 |
| 387 | |
| 388 | #endif |