| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Heiko Stuebner <heiko@sntech.de> |
| 11 | |
| 12 | properties: |
| 13 | compatible: |
| 14 | const: rockchip,rk3399-dwc3 |
| 15 | |
| 16 | '#address-cells': |
| 17 | const: 2 |
| 18 | |
| 19 | '#size-cells': |
| 20 | const: 2 |
| 21 | |
| 22 | ranges: true |
| 23 | |
| 24 | clocks: |
| 25 | items: |
| 26 | - description: |
| 27 | Controller reference clock, must to be 24 MHz |
| 28 | - description: |
| 29 | Controller suspend clock, must to be 24 MHz or 32 KHz |
| 30 | - description: |
| 31 | Master/Core clock, must to be >= 62.5 MHz for SS |
| 32 | operation and >= 30MHz for HS operation |
| 33 | - description: |
| 34 | USB3 aclk peri |
| 35 | - description: |
| 36 | USB3 aclk |
| 37 | - description: |
| 38 | Controller grf clock |
| 39 | |
| 40 | clock-names: |
| 41 | items: |
| 42 | - const: ref_clk |
| 43 | - const: suspend_clk |
| 44 | - const: bus_clk |
| 45 | - const: aclk_usb3_rksoc_axi_perf |
| 46 | - const: aclk_usb3 |
| 47 | - const: grf_clk |
| 48 | |
| 49 | resets: |
| 50 | maxItems: 1 |
| 51 | |
| 52 | reset-names: |
| 53 | const: usb3-otg |
| 54 | |
| 55 | patternProperties: |
| 56 | '^usb@': |
| 57 | $ref: snps,dwc3.yaml# |
| 58 | |
| 59 | additionalProperties: false |
| 60 | |
| 61 | required: |
| 62 | - compatible |
| 63 | - '#address-cells' |
| 64 | - '#size-cells' |
| 65 | - ranges |
| 66 | - clocks |
| 67 | - clock-names |
| 68 | - resets |
| 69 | - reset-names |
| 70 | |
| 71 | examples: |
| 72 | - | |
| 73 | #include <dt-bindings/clock/rk3399-cru.h> |
| 74 | #include <dt-bindings/power/rk3399-power.h> |
| 75 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 76 | |
| 77 | bus { |
| 78 | #address-cells = <2>; |
| 79 | #size-cells = <2>; |
| 80 | |
| 81 | usb { |
| 82 | compatible = "rockchip,rk3399-dwc3"; |
| 83 | #address-cells = <2>; |
| 84 | #size-cells = <2>; |
| 85 | ranges; |
| 86 | clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, |
| 87 | <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, |
| 88 | <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; |
| 89 | clock-names = "ref_clk", "suspend_clk", |
| 90 | "bus_clk", "aclk_usb3_rksoc_axi_perf", |
| 91 | "aclk_usb3", "grf_clk"; |
| 92 | resets = <&cru SRST_A_USB3_OTG0>; |
| 93 | reset-names = "usb3-otg"; |
| 94 | |
| 95 | usb@fe800000 { |
| 96 | compatible = "snps,dwc3"; |
| 97 | reg = <0x0 0xfe800000 0x0 0x100000>; |
| 98 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; |
| 99 | clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, |
| 100 | <&cru SCLK_USB3OTG0_SUSPEND>; |
| 101 | clock-names = "ref", "bus_early", "suspend"; |
| 102 | dr_mode = "otg"; |
| 103 | phys = <&u2phy0_otg>, <&tcphy0_usb3>; |
| 104 | phy-names = "usb2-phy", "usb3-phy"; |
| 105 | phy_type = "utmi_wide"; |
| 106 | snps,dis_enblslpm_quirk; |
| 107 | snps,dis-u2-freeclk-exists-quirk; |
| 108 | snps,dis_u2_susphy_quirk; |
| 109 | snps,dis-del-phy-power-chg-quirk; |
| 110 | snps,dis-tx-ipgap-linecheck-quirk; |
| 111 | power-domains = <&power RK3399_PD_USB3>; |
| 112 | }; |
| 113 | }; |
| 114 | }; |
| 115 | ... |