| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | MSM SoC HSUSB controllers |
| 2 | |
| 3 | EHCI |
| 4 | |
| 5 | Required properties: |
| 6 | - compatible: Should contain "qcom,ehci-host" |
| 7 | - regs: offset and length of the register set in the memory map |
| 8 | - usb-phy: phandle for the PHY device |
| 9 | |
| 10 | Example EHCI controller device node: |
| 11 | |
| 12 | ehci: ehci@f9a55000 { |
| 13 | compatible = "qcom,ehci-host"; |
| 14 | reg = <0xf9a55000 0x400>; |
| 15 | usb-phy = <&usb_otg>; |
| 16 | }; |
| 17 | |
| 18 | USB PHY with optional OTG: |
| 19 | |
| 20 | Required properties: |
| 21 | - compatible: Should contain: |
| 22 | "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY |
| 23 | "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY |
| 24 | |
| 25 | - regs: Offset and length of the register set in the memory map |
| 26 | - interrupts: interrupt-specifier for the OTG interrupt. |
| 27 | |
| 28 | - clocks: A list of phandle + clock-specifier pairs for the |
| 29 | clocks listed in clock-names |
| 30 | - clock-names: Should contain the following: |
| 31 | "phy" USB PHY reference clock |
| 32 | "core" Protocol engine clock |
| 33 | "iface" Interface bus clock |
| 34 | "alt_core" Protocol engine clock for targets with asynchronous |
| 35 | reset methodology. (optional) |
| 36 | |
| 37 | - vdccx-supply: phandle to the regulator for the vdd supply for |
| 38 | digital circuit operation. |
| 39 | - v1p8-supply: phandle to the regulator for the 1.8V supply |
| 40 | - v3p3-supply: phandle to the regulator for the 3.3V supply |
| 41 | |
| 42 | - resets: A list of phandle + reset-specifier pairs for the |
| 43 | resets listed in reset-names |
| 44 | - reset-names: Should contain the following: |
| 45 | "phy" USB PHY controller reset |
| 46 | "link" USB LINK controller reset |
| 47 | |
| 48 | - qcom,otg-control: OTG control (VBUS and ID notifications) can be one of |
| 49 | 1 - PHY control |
| 50 | 2 - PMIC control |
| 51 | |
| 52 | Optional properties: |
| 53 | - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" |
| 54 | |
| 55 | - switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual |
| 56 | SPDT USB Switch, witch is controlled by GPIO to de/multiplex |
| 57 | D+/D- USB lines between connectors. |
| 58 | |
| 59 | - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device |
| 60 | Mode Eye Diagram test. Start address at which these values will be |
| 61 | written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as |
| 62 | "do not overwrite default value at this address". |
| 63 | For example: qcom,phy-init-sequence = < -1 0x63 >; |
| 64 | Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1. |
| 65 | |
| 66 | - qcom,phy-num: Select number of pyco-phy to use, can be one of |
| 67 | 0 - PHY one, default |
| 68 | 1 - Second PHY |
| 69 | Some platforms may have configuration to allow USB |
| 70 | controller work with any of the two HSPHYs present. |
| 71 | |
| 72 | - qcom,vdd-levels: This property must be a list of three integer values |
| 73 | (no, min, max) where each value represents either a voltage |
| 74 | in microvolts or a value corresponding to voltage corner. |
| 75 | |
| 76 | - qcom,manual-pullup: If present, vbus is not routed to USB controller/phy |
| 77 | and controller driver therefore enables pull-up explicitly |
| 78 | before starting controller using usbcmd run/stop bit. |
| 79 | |
| 80 | - extcon: phandles to external connector devices. First phandle |
| 81 | should point to external connector, which provide "USB" |
| 82 | cable events, the second should point to external connector |
| 83 | device, which provide "USB-HOST" cable events. If one of |
| 84 | the external connector devices is not required empty <0> |
| 85 | phandle should be specified. |
| 86 | |
| 87 | Example HSUSB OTG controller device node: |
| 88 | |
| 89 | usb@f9a55000 { |
| 90 | compatible = "qcom,usb-otg-snps"; |
| 91 | reg = <0xf9a55000 0x400>; |
| 92 | interrupts = <0 134 0>; |
| 93 | dr_mode = "peripheral"; |
| 94 | |
| 95 | clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>, |
| 96 | <&gcc GCC_USB_HS_AHB_CLK>; |
| 97 | |
| 98 | clock-names = "phy", "core", "iface"; |
| 99 | |
| 100 | vddcx-supply = <&pm8841_s2_corner>; |
| 101 | v1p8-supply = <&pm8941_l6>; |
| 102 | v3p3-supply = <&pm8941_l24>; |
| 103 | |
| 104 | resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>; |
| 105 | reset-names = "phy", "link"; |
| 106 | |
| 107 | qcom,otg-control = <1>; |
| 108 | qcom,phy-init-sequence = < -1 0x63 >; |
| 109 | qcom,vdd-levels = <1 5 7>; |
| 110 | }; |