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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/renesas,hscif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF)
8
9maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11
12allOf:
13 - $ref: serial.yaml#
14
15properties:
16 compatible:
17 oneOf:
18 - items:
19 - enum:
20 - renesas,hscif-r8a7778 # R-Car M1
21 - renesas,hscif-r8a7779 # R-Car H1
22 - const: renesas,rcar-gen1-hscif # R-Car Gen1
23 - const: renesas,hscif # generic HSCIF compatible UART
24
25 - items:
26 - enum:
27 - renesas,hscif-r8a7742 # RZ/G1H
28 - renesas,hscif-r8a7743 # RZ/G1M
29 - renesas,hscif-r8a7744 # RZ/G1N
30 - renesas,hscif-r8a7745 # RZ/G1E
31 - renesas,hscif-r8a77470 # RZ/G1C
32 - renesas,hscif-r8a7790 # R-Car H2
33 - renesas,hscif-r8a7791 # R-Car M2-W
34 - renesas,hscif-r8a7792 # R-Car V2H
35 - renesas,hscif-r8a7793 # R-Car M2-N
36 - renesas,hscif-r8a7794 # R-Car E2
37 - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1
38 - const: renesas,hscif # generic HSCIF compatible UART
39
40 - items:
41 - enum:
42 - renesas,hscif-r8a774a1 # RZ/G2M
43 - renesas,hscif-r8a774b1 # RZ/G2N
44 - renesas,hscif-r8a774c0 # RZ/G2E
45 - renesas,hscif-r8a774e1 # RZ/G2H
46 - renesas,hscif-r8a7795 # R-Car H3
47 - renesas,hscif-r8a7796 # R-Car M3-W
48 - renesas,hscif-r8a77961 # R-Car M3-W+
49 - renesas,hscif-r8a77965 # R-Car M3-N
50 - renesas,hscif-r8a77970 # R-Car V3M
51 - renesas,hscif-r8a77980 # R-Car V3H
52 - renesas,hscif-r8a77990 # R-Car E3
53 - renesas,hscif-r8a77995 # R-Car D3
54 - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
55 - const: renesas,hscif # generic HSCIF compatible UART
56
57 - items:
58 - enum:
59 - renesas,hscif-r8a779a0 # R-Car V3U
60 - renesas,hscif-r8a779f0 # R-Car S4-8
61 - renesas,hscif-r8a779g0 # R-Car V4H
62 - const: renesas,rcar-gen4-hscif # R-Car Gen4
63 - const: renesas,hscif # generic HSCIF compatible UART
64
65 reg:
66 maxItems: 1
67
68 interrupts:
69 maxItems: 1
70
71 clocks:
72 minItems: 1
73 maxItems: 4
74
75 clock-names:
76 minItems: 1
77 maxItems: 4
78 items:
79 enum:
80 - fck # UART functional clock
81 - hsck # optional external clock input
82 - brg_int # optional internal clock source for BRG frequency divider
83 - scif_clk # optional external clock source for BRG frequency divider
84
85 power-domains:
86 maxItems: 1
87
88 resets:
89 maxItems: 1
90
91 dmas:
92 minItems: 2
93 maxItems: 4
94 description:
95 Must contain a list of pairs of references to DMA specifiers, one for
96 transmission, and one for reception.
97
98 dma-names:
99 minItems: 2
100 maxItems: 4
101 items:
102 enum:
103 - tx
104 - rx
105
106required:
107 - compatible
108 - reg
109 - interrupts
110 - clocks
111 - clock-names
112 - power-domains
113
114if:
115 properties:
116 compatible:
117 contains:
118 enum:
119 - renesas,rcar-gen2-hscif
120 - renesas,rcar-gen3-hscif
121 - renesas,rcar-gen4-hscif
122then:
123 required:
124 - resets
125
126unevaluatedProperties: false
127
128examples:
129 - |
130 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
131 #include <dt-bindings/interrupt-controller/arm-gic.h>
132 #include <dt-bindings/power/r8a7795-sysc.h>
133 aliases {
134 serial1 = &hscif1;
135 };
136
137 hscif1: serial@e6550000 {
138 compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif",
139 "renesas,hscif";
140 reg = <0xe6550000 96>;
141 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
143 <&scif_clk>;
144 clock-names = "fck", "brg_int", "scif_clk";
145 dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>;
146 dma-names = "tx", "rx", "tx", "rx";
147 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
148 resets = <&cpg 519>;
149 uart-has-rtscts;
150 };