| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Samsung S5P/Exynos SoC USB 2.0 PHY |
| 8 | |
| 9 | maintainers: |
| 10 | - Krzysztof Kozlowski <krzk@kernel.org> |
| 11 | - Marek Szyprowski <m.szyprowski@samsung.com> |
| 12 | - Sylwester Nawrocki <s.nawrocki@samsung.com> |
| 13 | |
| 14 | description: | |
| 15 | The first phandle argument in the PHY specifier identifies the PHY, its |
| 16 | meaning is compatible dependent. For the currently supported SoCs (Exynos4210 |
| 17 | and Exynos4212) it is as follows:: |
| 18 | 0 - USB device ("device"), |
| 19 | 1 - USB host ("host"), |
| 20 | 2 - HSIC0 ("hsic0"), |
| 21 | 3 - HSIC1 ("hsic1"), |
| 22 | Exynos3250 has only USB device phy available as phy 0. |
| 23 | |
| 24 | Exynos4210 and Exynos4212 use mode switching and require that mode switch |
| 25 | register is supplied. |
| 26 | |
| 27 | properties: |
| 28 | compatible: |
| 29 | enum: |
| 30 | - samsung,exynos3250-usb2-phy |
| 31 | - samsung,exynos4210-usb2-phy |
| 32 | - samsung,exynos4x12-usb2-phy |
| 33 | - samsung,exynos5250-usb2-phy |
| 34 | - samsung,exynos5420-usb2-phy |
| 35 | - samsung,s5pv210-usb2-phy |
| 36 | |
| 37 | clocks: |
| 38 | items: |
| 39 | - description: PHY module gate clock. |
| 40 | - description: Reference rate clock of PHY module. |
| 41 | |
| 42 | clock-names: |
| 43 | items: |
| 44 | - const: phy |
| 45 | - const: ref |
| 46 | |
| 47 | "#phy-cells": |
| 48 | const: 1 |
| 49 | |
| 50 | reg: |
| 51 | maxItems: 1 |
| 52 | |
| 53 | samsung,pmureg-phandle: |
| 54 | $ref: /schemas/types.yaml#/definitions/phandle |
| 55 | description: |
| 56 | Phandle to PMU system controller interface. |
| 57 | |
| 58 | samsung,sysreg-phandle: |
| 59 | $ref: /schemas/types.yaml#/definitions/phandle |
| 60 | description: |
| 61 | Phandle to system registers interface. |
| 62 | |
| 63 | vbus-supply: |
| 64 | description: |
| 65 | VBUS power source. |
| 66 | |
| 67 | required: |
| 68 | - compatible |
| 69 | - clocks |
| 70 | - clock-names |
| 71 | - "#phy-cells" |
| 72 | - reg |
| 73 | - samsung,pmureg-phandle |
| 74 | |
| 75 | allOf: |
| 76 | - if: |
| 77 | properties: |
| 78 | compatible: |
| 79 | contains: |
| 80 | enum: |
| 81 | - samsung,exynos4x12-usb2-phy |
| 82 | - samsung,exynos5250-usb2-phy |
| 83 | - samsung,exynos5420-usb2-phy |
| 84 | then: |
| 85 | required: |
| 86 | - samsung,sysreg-phandle |
| 87 | |
| 88 | additionalProperties: false |
| 89 | |
| 90 | examples: |
| 91 | - | |
| 92 | #include <dt-bindings/clock/exynos5420.h> |
| 93 | |
| 94 | phy@12130000 { |
| 95 | compatible = "samsung,exynos5420-usb2-phy"; |
| 96 | reg = <0x12130000 0x100>; |
| 97 | #phy-cells = <1>; |
| 98 | clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; |
| 99 | clock-names = "phy", "ref"; |
| 100 | samsung,sysreg-phandle = <&sysreg_system_controller>; |
| 101 | samsung,pmureg-phandle = <&pmu_system_controller>; |
| 102 | }; |