blob: 808e90b2465d9d1eb351dfad6e5ffd9613dde2ab [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Broadcom Cygnus PCIe PHY
8
9maintainers:
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
12
13properties:
14 $nodename:
15 pattern: "^pcie[-|_]phy(@.*)?$"
16
17 compatible:
18 items:
19 - const: brcm,cygnus-pcie-phy
20
21 reg:
22 maxItems: 1
23 description: >
24 Base address and length of the PCIe PHY block
25
26 "#address-cells":
27 const: 1
28
29 "#size-cells":
30 const: 0
31
32patternProperties:
33 "^pcie-phy@[0-9]+$":
34 type: object
35 additionalProperties: false
36 description: >
37 PCIe PHY child nodes
38
39 properties:
40 reg:
41 maxItems: 1
42 description: >
43 The PCIe PHY port number
44
45 "#phy-cells":
46 const: 0
47
48 required:
49 - reg
50 - "#phy-cells"
51
52required:
53 - compatible
54 - reg
55 - "#address-cells"
56 - "#size-cells"
57
58additionalProperties: false
59
60examples:
61 - |
62 pcie_phy: pcie_phy@301d0a0 {
63 compatible = "brcm,cygnus-pcie-phy";
64 reg = <0x0301d0a0 0x14>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 pcie0_phy: pcie-phy@0 {
69 reg = <0>;
70 #phy-cells = <0>;
71 };
72
73 pcie1_phy: pcie-phy@1 {
74 reg = <1>;
75 #phy-cells = <0>;
76 };
77 };